Senior DFT Engineer - CA, Santa Clara, United States
Originally posted 17 August 2026 by the employer.
Work on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation.
About the role
As a Senior DFT Engineer, you will contribute to Design-for-Test Engineering, focusing on DFT architecture, verification, and post-silicon validation for complex semiconductor chips.
What you'll do
- Define, prototype, and deploy DFX architectures and methodologies, including high speed test access architectures and in-system-test architecture.
- Craft key DFX architecture and methodologies to meet system level safety diagnostic test quality, in-field test quality, advanced defect screening, and diagnosis.
- Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI, SW development, and Operations.
- Mentor junior engineers on test designs and trade-offs.
What you'll need
- BSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years of experience in DFT or related domains.
- Expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation.
- Analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools.
- Exposure to cross functional areas including RTL & clocks design, STA, place-n-route, and power.
- Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
- Programming and scripting skills in Perl, Python, or Tcl.
This role has been open 59 days — slightly above the 57-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
242
|
Median days open
57 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (242 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 23 | 242 |
| Open roles in the wider Digital Design & Verification family | 235 | 3198 · 115 employers |
| Median days open | 34 d | 57 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD · 39 open roles · median 43 d
- NVIDIA (this employer) · 23 open roles · median 35 d
- Qualcomm · 23 open roles · median 100 d
- NXP Semiconductors · 18 open roles · median 65 d
- Synopsys · 14 open roles · median 24 d
- Micron Technology · 10 open roles · median 64 d
How we counted: 242 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.