Senior Design Verification Engineer - Santa Clara, CA, United States
$200,000 - $500,000 USD yearly
Originally posted 15 July 2026 by the employer.
Verify Velaura’s Physical AI SoC.
About the role
This role involves verifying complex hardware blocks and system-level behavior across the entire platform for Velaura’s Physical AI SoC.
What you'll do
- Develop and execute verification strategies for key portions of the SoC.
- Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, and emulation.
- Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.
- Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.
- Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.
- Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.
What you'll need
- 10+ Years of experience verifying complex digital systems.
- Strong understanding of computer architecture, microarchitecture, SoC architecture, and digital design fundamentals.
- Experience in understanding low power methodologies and verification criteria.
- Strong understanding of CDC issues, clocking and reset verification.
- Experience with SystemVerilog, UVM, C/C++, assertions, and coverage-driven verification.
- Familiarity with formal verification techniques and tools.
- Experience with emulation, FPGA prototyping, or pre-silicon validation environments.
- Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures.
- Experience debugging complex system-level issues.
Nice to have
- Experience with one or more of the following standards: ISO 26262, IEC 61508, IEC 61511, ISO 13849.
- Experience with AI, machine learning, or edge AI hardware.
- Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
- Experience verifying QoS, latency-sensitive, or real-time systems.
- Experience with HW/SW co-verification and system-level validation.
- Exposure to performance modeling, profiling, and workload characterization.
- Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and ADAS platforms, aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.
Skills: verification strategies, SystemVerilog UVM, formal verification, HW/SW co-verification, SoC infrastructure
This role has been open 84 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1201
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (1201 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 1201 |
| Open roles in the wider Digital Design & Verification family | 26 | 3201 · 115 employers |
| Median days open | 32 d | 66 d (−34 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: verification strategies, SystemVerilog UVM, formal verification, HW/SW co-verification, SoC infrastructure
Who's hiring in this category
- Qualcomm · 110 open roles · median 40 d
- AMD · 95 open roles · median 52 d
- NVIDIA · 84 open roles · median 60 d
- Synopsys · 64 open roles · median 34 d
- SiFive · 55 open roles · median 76 d
- Cadence Design Systems · 50 open roles · median 118 d
How we counted: 1201 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.