Senior Design Verification Engineer - California, Santa Clara, United States

Originally posted 16 July 2026 by the employer.

About the role

Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team to own end-to-end verification of chassis and interconnect IP blocks from planning through signoff. The role focuses on testbench architecture, test plan execution, and coverage closure across interconnects, caches, and memory subsystems.

What you'll do

- Own verification planning and execution for key IP features across IP and subsystem integration points. - Build scalable verification environments and targeted test plans with reusable testbenches, checkers, VIPs, and behavioral models. - Collaborate with architecture, design, and software teams from specification through bringup, taking responsibility for functional signoffs and performance/power metrics. - Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies, evaluating ML-driven verification flows. - Mentor and develop verification engineers while establishing verification best practices and delivering reusable verification collateral.

What you'll need

- Bachelor of Science Degree in Electrical or Computer Engineering, Computer Science, or a STEM-related field. - 10+ years of experience in design verification (DV), with a background in IP DV, subsystem, and SoC-level verification. - Experience in interconnects, caches, and memory subsystems, including bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL, as well as cache coherency and memory consistency models. - Experience verifying global functions including debug, trace, clock and power management, RAS, QoS, and security features. - Experience in simulation and formal verification methodologies including UVM, SVA, ABV, co-simulation, and low-power verification techniques. - Hands-on coding experience across SystemVerilog/UVM, C/C++, Python, build systems, and EDA tool flows across RTL, physical design, and CAD.

Nice to have

- Post-graduate degree in Electrical or Computer Engineering, Computer Science, or a STEM-related field. - Experience with formal verification tools such as JasperGold or VC Formal, alongside emulation or FPGA-based verification. - Experience with system IPs such as MMUs (SMMU or IOMMU), interrupt controllers, and associated software stacks.

Skills: DV methodologies, protocol verification, memory subsystem, UVM