Senior Design Verification Engineer - Austin, United States
$124,600 - $231,400 USD yearly
Originally posted 2 October 2026 by the employer.
About the role
As a Senior Design Verification Engineer, you will be responsible for ensuring the functional correctness and performance of digital modem designs used in Silicon Labs’ low-power wireless products. This role focuses on building efficient, high-performance digital systems that enable wireless connectivity.
What you'll do
- Define and execute verification strategies for digital modem designs across key wireless use cases.
- Develop and maintain scalable verification environments using SystemVerilog/UVM or similar methodologies.
- Create test plans, test benches, and stimuli to achieve high functional and coverage closure.
- Debug and analyze design issues, working closely with design and architecture teams to resolve them.
- Track and drive functional and code coverage to ensure verification completeness.
- Support silicon bring-up and correlate pre-silicon verification with post-silicon results.
What you'll need
- BSEE/CE or a related field.
- Solid understanding of digital design fundamentals and verification concepts.
- 3-6 years of experience in digital design verification, with a focus on modem or wireless PHY designs.
- Experience with SystemVerilog and UVM or similar verification methodologies.
- Strong debugging skills with experience analyzing simulation results and identifying root causes.
- Familiarity with scripting languages such as Python or Perl for automation.
- Basic understanding of wireless communication systems or digital signal processing concepts.
Nice to have
- Experience verifying wireless standards such as BLE, Wi-Fi, Zigbee, or similar technologies.
- Experience with constrained-random, coverage-driven verification, and SystemVerilog assertions (SVA).
- Familiarity with C/C++ or MATLAB for algorithm modeling and reference model development.
- Experience with mixed-signal or system-level verification, including co-simulation with analog/RF components.
- Exposure to post-silicon validation, lab bring-up, and correlation with pre-silicon results.
- Experience with low-power design verification and power-aware methodologies.
Skills: functional correctness, SystemVerilog/UVM, test plans, test benches, functional and code coverage
This role has been open 7 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1206
|
Median days open
63 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Silicon Labs | All employers we track in this specialty (1206 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 1206 |
| Open roles in the wider Digital Design & Verification family | 19 | 3183 · 114 employers |
| Median days open | 35 d | 63 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: functional correctness, SystemVerilog/UVM, test plans, test benches, functional and code coverage
Who's hiring in this category
- Qualcomm · 111 open roles · median 42 d
- AMD · 102 open roles · median 49 d
- NVIDIA · 76 open roles · median 62 d
- Synopsys · 61 open roles · median 25 d
- SiFive · 55 open roles · median 66 d
- Micron Technology · 52 open roles · median 98 d
How we counted: 1206 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.