Senior Debug Verification Engineer - San Jose, California, United States
$149,100 - $215,000 USD yearly
Originally posted 29 September 2026 by the employer.
About the role
As a Senior Debug Verification Engineer, you will handle Design for Debug architecture verification tasks, including creating test cases and testbenches using UVM methodology. The scope spans pre-silicon SoC, FPGA, and full-chip design functional verification to achieve full coverage.
What you'll do
- Execute pre-silicon system verification across SoC, FPGA, and full-chip designs. - Create test cases and testbenches using UVM methodology. - Define verification strategies, methodologies, and test plans to enable full-chip and system functional verification. - Perform design verification for Design for Debug architecture, covering JTAG, high-speed USB, PCIe-based debug, and internal signal visualization. - Coordinate cross-functional verification efforts with Design, SW, and Architecture teams to reach full coverage and identify performance shortfalls.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. - 8+ years of experience with complex ASIC designs and/or verification. - 8+ years of experience with the SystemVerilog language. - 8+ years of experience with UVM verification methodology and formal verification methods. - 8+ years of experience scripting in Linux/Unix environments.
Nice to have
- Experience with ARM and RISC Debug Architectures with a focus on design verification. - Prior working experience with UltraSoC or Tessent Embedded Analytics Debug Architecture. - Experience with hardware emulation. - Proficiency in Perl and/or Python scripting.
This role has been open 24 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Altera | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1254 |
| Open roles in the wider Digital Design & Verification family | 21 | 3328 · 115 employers |
| Median days open | 87 d | 64 d (+23 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.