Originally posted 24 September 2026 by the employer.
About the role
This role involves owning block- and subsystem-level design verification for advanced out-of-order CPU cores. You will verify complex Front end Designs including branch prediction, Instruction decodes, execution pipelines, memory systems, and coherence protocols.
What you'll do
- Drive verification for key out-of-order CPU blocks such as front-end, rename, issue queues, execution units, reorder buffer, load-store unit, and L1 caches.
- Derive verification plans from architecture and micro-architecture specifications, with emphasis on speculative execution flows, pipeline hazards, memory ordering, and cache hierarchy interaction.
- Develop and maintain SystemVerilog/UVM testbenches, including UVM agents, monitors, scoreboards, and reference models.
- Implement constrained-random stimulus and directed tests for out-of-order corner cases and self-checking mechanisms for instruction retirement and architectural state.
- Define and track functional, code, and assertion coverage, identifying gaps and adding tests/monitors to achieve closure.
- Create and maintain SVA assertions for key micro-architectural properties and debug complex failures in speculation, load-store ordering, and TLB/MMU corner cases.
What you'll need
- BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 5–10 years of ASIC/SoC/IP design verification experience.
- Direct experience verifying out-of-order or superscalar CPU cores.
- Strong proficiency in System Verilog and UVM.
- Solid understanding of CPU micro-architecture, including fetch/decode, rename, ROB, issue/execute, bypassing, commit, LSU, store buffer, atomics/LR-SC, fences, memory ordering, L1 caches, TLBs, page-table walkers, and basic coherence concepts.
- Hands-on experience with constrained-random and coverage-driven verification.
- Experience writing and debugging SVA assertions.
- Hands-on experience with industry-standard simulators (e.g., VCS, Xcelium, Questa) and debug tools (e.g., Verdi/DVE).
Skills: SystemVerilog, UVM, CPU micro-architecture, coverage-driven verification, SVA assertions
More semiconductor jobs: SiFive jobs · Verification engineer jobs · India jobs
This role has been open 42 days — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1317
|
Median days open
57 d
|
Category median salary (all employers)
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiFive | All employers we track in this specialty (1317 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 58 | 1317 |
| Open roles in the wider Digital Design & Verification family | 87 | 3497 · 120 employers |
| Median days open | 63 d | 57 d (+6 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: SystemVerilog, UVM, CPU micro-architecture, coverage-driven verification, SVA assertions
Who's hiring in this category
- Qualcomm · 117 open roles · median 49 d
- NVIDIA · 104 open roles · median 71 d
- Apple · 99 open roles · median 9 d
- AMD · 83 open roles · median 65 d
- Synopsys · 73 open roles · median 50 d
- SiFive (this employer) · 58 open roles · median 63 d
How we counted: 1317 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.