Senior Chip Lead Engineer-SoC/ASIC - CA, San Jose, United States
Originally posted 3 September 2026 by the employer.
About the role
This role is for an experienced ASIC/FPGA design engineer to broaden their scope and deepen their influence across the entire chip development spectrum, from architecture through production shipment. You will serve as a technical partner to chip leads across cross-functional teams to solve complex technical challenges.
What you'll do
- Lead chip design initiatives from architectural concept through production release.
- Provide technical guidance across all phases of the chip development lifecycle.
- Drive technical decisions in ambiguous and rapidly evolving project environments.
- Partner with chip leads and program managers to support scheduling, resource planning, and risk mitigation.
- Identify and resolve complex technical challenges throughout the design flow.
- Drive continuous improvement in design methodologies, development processes, and engineering practices.
What you'll need
- 10+ years of semiconductor industry experience.
- 8+ years of hands-on ASIC and/or FPGA design experience.
- Demonstrated experience across multiple phases of chip development including architecture definition, RTL development, verification, physical design, and silicon validation.
- Deep technical expertise in one or more semiconductor disciplines combined with a broad understanding of the full chip development lifecycle.
- Strong knowledge of SoC and subsystem architecture, RTL design and synthesis, verification methodologies, physical design principles, timing closure, and power optimization techniques.
- Proficiency with Verilog, VHDL, and/or SystemVerilog.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
Nice to have
- Experience with advanced process nodes (7nm and below).
- Exposure to multiple chip architectures including CPU, GPU, FPGA, AI/ML accelerators, and networking devices.
- Background spanning both ASIC and FPGA development.
- Experience interacting directly with customers, vendors, foundries, and external partners.
- Prior technical leadership, mentoring, team leadership, or management experience.
- Master's degree preferred.
Skills: ASIC/FPGA design, chip development lifecycle, architecture definition, physical design, silicon validation
This role has been open 41 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
470
|
Median days open
79 d
|
Median salary
$235k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (470 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 470 |
| Open roles in the wider Digital Design & Verification family | 255 | 3188 · 115 employers |
| Median days open | 64 d | 79 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $235k |
Skills observed across this category: ASIC/FPGA design, chip development lifecycle, architecture definition, physical design, silicon validation
Who's hiring in this category
- Qualcomm · 72 open roles · median 86 d
- NVIDIA · 56 open roles · median 68 d
- Apple · 39 open roles · median 9 d
- AMD (this employer) · 35 open roles · median 64 d
- Arm Holdings · 27 open roles · median 112 d
- NXP Semiconductors · 21 open roles · median 114 d
How we counted: 470 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.