Senior Characterization and Test Engineer - Milpitas, California, United States
$151,800 USD yearly
Originally posted 27 August 2026 by the employer.
Focused on silicon photonics.
About the role
The Senior Characterization & Test Engineer will own the evaluation, characterization, and validation strategy for photonic devices, packages, and subsystems. This role will lead the design and execution of electrical, optical, thermal, and mechanical test programs, driving root-cause and reliability investigations.
What you'll do
- Lead electrical, optical, thermal, and mechanical characterization programs for photonic devices, packages, and assemblies.
- Own the design of test plans and DOEs supporting product development, process validation, reliability qualification, and failure analysis.
- Drive selection, setup, and qualification of laboratory equipment, including optical measurement systems, vibrometers, thermal imaging systems, and mechanical testers.
- Analyze and interpret complex test data, identify performance and reliability trends, and translate findings into engineering recommendations.
- Lead root-cause investigations and failure analysis efforts, coordinating across characterization, packaging, reliability, and manufacturing.
- Develop and maintain automated test scripts, data pipelines, and analysis tools (Python or similar).
What you'll need
- Bachelor's degree in Mechanical Engineering, Optical Engineering, Applied Physics, or a related discipline with 8+ years of relevant experience, or Master's degree with 5+ years of relevant experience, in engineering characterization, testing, laboratory operations, or product development.
- Demonstrated hands-on expertise operating and troubleshooting characterization equipment including Infrared Thermography, Laser Doppler Vibrometers (LDV), Instron Universal Mechanical Testers, and C-Mode Scanning Acoustic Microscopy (C-SAM).
- Track record of independently analyzing thermal, mechanical, vibration, and package integrity data.
- Deep experience with laboratory instrumentation and data acquisition system design/integration.
- Solid working knowledge of optics, photonics, electronics, semiconductor devices, or advanced packaging technologies.
- Proficiency with data analysis tools such as Python, MATLAB, JMP, or equivalent, including building automated analysis pipelines.
- Strong command of Design of Experiments (DOE) and statistical analysis methods, with experience designing test programs.
Nice to have
- Direct experience with photonic devices, optoelectronics, semiconductor packaging, or advanced manufacturing.
- Experience with optical alignment, imaging systems, or optical characterization technique development.
- Experience building test automation frameworks or new test capability from scratch.
- Experience leading reliability testing or failure analysis programs, including ownership of qualification test plans.
This role has been open 49 days — well above the 28-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
542
|
Median days open
28 d
|
Median salary
$172k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | PsiQuantum | All employers we track in this specialty (542 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 542 |
| Open roles in the wider Silicon Validation & Test family | 8 | 2216 · 112 employers |
| Median days open | 25 d | 28 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $172k |
Who's hiring in this category
- Teradyne · 72 open roles · median 27 d
- Renesas Electronics · 45 open roles · median 22 d
- Infineon Technologies · 41 open roles · median 37 d
- Micron Technology · 27 open roles · median 35 d
- Qualcomm · 27 open roles · median 27 d
- AMD · 25 open roles · median 42 d
How we counted: 542 open Silicon Test Engineering (DFT Test) roles from 76 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.