Senior ASIC Verification Engineer - GPU - CA, Santa Clara, United States
$168,000 - $264,500 USD yearly
Originally posted 23 September 2026 by the employer. Relisted by the employer on 24 September 2026.
About the role
As a Senior ASIC Verification Engineer - GPU, you will verify the design and implementation of GPUs powering consumer graphics and AI applications.
What you'll do
- Verify the ASIC build, architecture, golden models, and micro-architecture using advanced verification methodologies such as UVM or equivalent. - Understand the design and implementation of your unit, cluster, or chip, define the verification scope, and develop verification infrastructure. - Verify the functional correctness of the design using test bench environments for unit- and system-level verification. - Collaborate with architects, designers, and pre- and post-silicon verification teams.
What you'll need
- Bachelor's Degree in EE, CS, or CE or equivalent experience. - 5+ years of relevant experience. - Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies. - Expertise in SystemVerilog or similar HVL. - Experience with design and verification tools such as VCS or equivalent simulation tools, and debug tools including Verdi, Indago, or GDB. - Experience crafting test bench environments for unit- and system-level verification.
Nice to have
- Perl and C/C++ programming language experience.
Skills: ASIC Verification, GPU, UVM, SystemVerilog, functional coverage
This role has been open 200 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1259
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1259 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 91 | 1259 |
| Open roles in the wider Digital Design & Verification family | 229 | 3310 · 115 employers |
| Median days open | 64 d | 65 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC Verification, GPU, UVM, SystemVerilog, functional coverage
Who's hiring in this category
- Qualcomm · 120 open roles · median 44 d
- NVIDIA (this employer) · 93 open roles · median 65 d
- AMD · 92 open roles · median 54 d
- Synopsys · 65 open roles · median 40 d
- SiFive · 55 open roles · median 82 d
- Cadence Design Systems · 52 open roles · median 124 d
How we counted: 1259 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.