Senior ASIC Verification Engineer - CA, Santa Clara, United States
$136,000 - $264,500 USD yearly
Originally posted 20 August 2026 by the employer.
ARM-based System on-chip backbone IPs for automotive and gaming console platforms.
About the role
As a Senior ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of SoCs and GPUs to ensure first-pass silicon success. The team focuses on the backbone IPs for ARM-based System on-chip devices across automotive and gaming console platforms.
What you'll do
- Lead the verification of ASIC design, architecture, golden models, and micro-architecture using methodologies such as UVM. - Define verification scope and develop verification infrastructure to verify complex logic. - Collaborate with architects, designers, and both pre- and post-silicon verification teams to achieve comprehensive coverage. - Incorporate AI and LLM-driven workflows into the verification cycle to optimize testbench generation, debug productivity, and coverage closure.
What you'll need
- BS or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science. - 5+ years of experience in ASIC verification-related fields at both the IP and SoC level. - Proven experience building UVM testbenches from scratch and applying constrained random methodology in a production environment. - High proficiency in C/C++ to develop architectural golden models and hardware-software co-verification tests. - Domain knowledge in Low-Speed IOs (QSPI, UART, I2C), High-Speed IOs (Ethernet), AXI/APB interconnects, DMA controllers, and Memory Controllers. - Experience with assertion-based design checks (SVA), code coverage, functional coverage, formal test plan documentation, and scripting in Python, Perl, or TCL.
Nice to have
- Advanced degrees (MS, PhD). - Advanced UVM architecture knowledge and large-scale SoC verification experience. - Demonstrated ability to use AI tools for engineering tasks. - Experience with Testbench Build flows, Makefiles, and version control (Perforce).
Skills: ASIC Verification, UVM testbenches, constrained random methodology, SoCs, GPUs
This role has been open 64 days — exactly the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 93 | 1254 |
| Open roles in the wider Digital Design & Verification family | 239 | 3328 · 115 employers |
| Median days open | 64 d | 64 d (same as this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC Verification, UVM testbenches, constrained random methodology, SoCs, GPUs
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD · 94 open roles · median 53 d
- NVIDIA (this employer) · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.