Senior ASIC Timing Engineer
$136,000 - $264,500 USD yearly
Originally posted 5 October 2026 by the employer.
About the role
This role involves leading timing analysis and closure processes for GPUs, CPUs, LPUs, and SoCs at block, cluster, and full chip levels.
What you'll do
- Drive timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs.
- Collaborate with RTL, DFX, and Clocks teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence.
- Implement ECOs.
- Leverage expertise to improve timing convergence flows in collaboration with methodology teams.
What you'll need
- BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 3 years’ experience in Timing and STA.
- Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
- Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
- Experience in physical design and optimization e.g., synthesis, placement, routing, logic restructuring.
- Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
- Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.
Skills: timing analysis, timing closure, STA, ECOs, deep sub-micron
This role has been open 0 days — well below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
631
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (631 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 631 |
| Open roles in the wider Physical Implementation family | 87 | 1430 · 108 employers |
| Median days open | 60 d | 60 d (same as this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: timing analysis, timing closure, STA, ECOs, deep sub-micron
Who's hiring in this category
- Qualcomm · 122 open roles · median 38 d
- AMD · 49 open roles · median 21 d
- Broadcom · 40 open roles · median 85 d
- NVIDIA (this employer) · 37 open roles · median 60 d
- Synopsys · 29 open roles · median 48 d
- Micron Technology · 25 open roles · median 75 d
How we counted: 631 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 6 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.