Senior ASIC RTL Design Engineer, AI Hardware - Sunnyvale, CA, United States
$200,000 - $290,000 USD yearly
Originally posted 24 September 2026 by the employer.
About the role
As a senior front-end design engineer, you will be a key part of the team designing and developing the Cerebras Wafer Scale Engine (WSE).
What you'll do
- Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
- Work closely with physical design team members for design closure to meet PPA goals.
- Work closely with Design verification and DFT teams for achieving functional and test coverage.
- Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
- Debug silicon-level functional, timing, and power issues during bring up.
What you'll need
- Master’s degree in Computer Science, Electrical Engineering, or equivalent.
- 8+ years of experience in delivering complex, high performance high quality RTL designs.
- Experience with Front End Chip integration and third-party IP integration.
- Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning or related fields.
- Proven track record of multiple silicon success.
- Experience collaborating with external vendors.
- Networking stack experience including TCP/IP, RDMA and Ethernet.
- Knowledge of PCIe, CPU interfaces and Serdes technology.
- Working knowledge of scripting tools: Python, TCL.
Nice to have
- Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis.
- Experience managing external ASIC vendor through product development cycle.
This role has been open 15 days — well below the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1019
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Cerebras | All employers we track in this specialty (1019 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1019 |
| Open roles in the wider Digital Design & Verification family | 6 | 3166 · 114 employers |
| Median days open | 46 d | 60 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 139 open roles · median 60 d
- Synopsys · 86 open roles · median 24 d
- AMD · 73 open roles · median 34 d
- Analog Devices · 50 open roles · median 41 d
- NXP Semiconductors · 48 open roles · median 78 d
- NVIDIA · 46 open roles · median 64 d
How we counted: 1019 open Digital/RTL Design (RTL Design) roles from 98 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.