Senior ASIC Design Verification Engineer - LPU
$168,000 - $310,500 USD yearly
Originally posted 22 September 2026 by the employer.
About the role
This role involves verifying the design and implementation of an inference accelerator.
What you'll do
- Verify the design and implementation of the inference accelerator.
- Be responsible for verification of the ASIC design, architecture, reference models, and micro-architecture using advanced verification methodologies.
- Define the verification scope, develop the verification infrastructure, and verify the correctness of the design.
- Implement and optimize automated verification flows.
What you'll need
- Bachelor's Degree in EE, CS, or CE (or equivalent experience) and 8+ years of relevant industry experience.
- Background with building block and SoC level testbench.
- Experience in verification using random stimulus, functional coverage, and assertion-based verification methodologies and tools.
- Expertise in SystemVerilog and Universal Verification Methodology (UVM).
- Experience with design and verification tools (VCS, Verdi or equivalent).
- Knowledge of ASIC design flow, from specification to GDS.
Nice to have
- Background in UPF power verification.
- Experience in netlist and DFT verification.
- Perl/Python and C/C++ programming language experience.
- Knowledge of applying machine learning to ASIC verification flow.
Skills: ASIC verification, SystemVerilog, UVM, random stimulus, functional coverage, assertion-based verification
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1168
|
Median days open
58 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1168 roles · 94 employers) |
|---|---|---|
| Open roles in this specialty | 88 | 1168 |
| Open roles in the wider Digital Design & Verification family | 244 | 3096 · 114 employers |
| Median days open | 69 d | 58 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: ASIC verification, SystemVerilog, UVM, random stimulus, functional coverage, assertion-based verification
Who's hiring in this category
- Qualcomm · 111 open roles · median 47 d
- AMD · 105 open roles · median 35 d
- NVIDIA (this employer) · 86 open roles · median 69 d
- Synopsys · 64 open roles · median 18 d
- SiFive · 54 open roles · median 50 d
- Micron Technology · 53 open roles · median 105 d
How we counted: 1168 open Design Verification (Design Verification) roles from 94 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.