Senior ASIC Design Verification Engineer (AI Compute) - San Jose, California, United States
Originally posted 16 October 2026 by the employer.
Verify the AI Persimmons inference chiplet.
About the role
As a Senior ASIC Design Verification Engineer, you will own verification of the AI Persimmons inference chiplet. This role involves collaborating daily with design, algorithm, and compiler teams to ensure silicon matches its intended feature set and is free of critical bugs before tape-out.
What you'll do
- Lead verification planning and execution from subsystem to full chip.
- Design and implement UVM testbenches with constrained-random stimulus, compute reference models, and scoreboards.
- Drive coverage closure using code, functional, and formal coverage.
- Develop and validate C/C++ firmware tests running on RISC-V cores.
- Extend verification with FPGA prototyping on Synopsys HAPS.
- Use AI agents for testbench generation, stimulus creation, regression triage, log analysis, and coverage closure.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
- 5+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across IP blocks, SoCs, and system-level designs.
- Verification experience on compute and fabric datapaths.
- Advanced SystemVerilog/Verilog and UVM, plus C/C++ embedded code development and validation on RISC-V or similar processors.
- A track record of scalable verification flows, coverage-driven strategies, assertion-based and formal verification.
- Experience building AI-driven workflows for regression triage, log analysis, or testbench generation.
Skills: ASIC Design Verification, AI inference chiplet, UVM testbenches, constrained-random stimulus, coverage closure, formal verification
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1195
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | persimmons | All employers we track in this specialty (1195 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1195 |
| Open roles in the wider Digital Design & Verification family | 2 | 3198 · 115 employers |
| Median days open | 0 d | 64 d (−64 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: ASIC Design Verification, AI inference chiplet, UVM testbenches, constrained-random stimulus, coverage closure, formal verification
Who's hiring in this category
- Qualcomm · 109 open roles · median 37 d
- AMD · 97 open roles · median 51 d
- NVIDIA · 84 open roles · median 58 d
- Synopsys · 63 open roles · median 31 d
- SiFive · 55 open roles · median 73 d
- Arm Holdings · 49 open roles · median 101 d
How we counted: 1195 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.