Digital Design & SoC Architecture
Memory & Storage Technologies
$136,000 - $264,500 USD yearly
Design and implement memory controllers for Tegra SoCs.
Originally posted November 13, 2026 by the employer.
About the role
As a Senior ASIC Design Engineer on the Memory Controller team, you will design and implement memory controllers for Tegra SoCs. You will work within the Memory Subsystem Design team alongside architects, software engineers, and circuit designers.
What you'll do
- Define micro-architecture and develop RTL design for memory controllers.
- Perform synthesis, functional verification, and timing analysis using CAD tools.
- Work across ASIC design flow stages including formal verification, emulation, power estimation, and ECO.
- Collaborate with architects, software engineers, and circuit designers to deliver memory subsystem solutions for SoCs and graphics controllers.
What you'll need
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related degree (or equivalent experience).
- 5+ years of ASIC design experience with a background in DRAM memory or processor design (Graphics, Microprocessors, Network Processors, or Mobile / Multimedia SOCs).
- Extensive experience in micro-architecture and RTL development.
- Relevant experience with ASIC design flow stages including functional and formal verification, emulation, synthesis & timing analysis, power estimation, and ECO.
- Strong understanding of Verilog or System Verilog.
- Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, and CMOS transistors and circuits.
- Programming skills in C and/or PERL/PYTHON.
Skills: ASIC, RTL, Verilog, micro-architecture, DRAM, memory controller
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