Senior ASIC Design Engineer, Low Power AI - Markham, Ontario, Canada
$108,000 - $158,000 USD yearly
Originally posted 15 September 2026 by the employer — open 4 days.
About the role
This role involves ASIC hardware design and implementation for low power AI subsystems within audio products.
What you'll do
- Develop micro-architecture and module specifications for digital audio and AI IP blocks that interface with the SoC.
- Implement modules and sub-systems and integrate IP from other teams in Verilog RTL.
- Analyze performance, area, power, and system cost tradeoffs for different implementations.
- Review opportunities for power optimization for ultra-low power designs.
- Work with the design verification team to debug tests at module, sub-system, and SoC levels throughout the ASIC development cycle.
- Work with the implementation team to review synthesis results, power metrics, and reach static timing closure.
What you'll need
- 2+ years of professional industry ASIC hardware design and/or implementation experience.
- Verilog/VHDL RTL design languages and ability to write clean, readable, synthesizable RTL.
- Understanding of ASIC/VLSI concepts.
- Experience in logic synthesis using Synopsis and/or Cadence tools.
- Ability to work legally in Canada.
Nice to have
- Experience with power analysis, power modeling, and low power RTL design.
- Experience with clock domain crossing techniques.
- Power and performance experience with an audio IP core, DSP, various audio interfaces (I2S, PCM, SLIMbus, SoundWire, Audio Codec), and accelerators (low-power AI/ML inference).
- Experience with a subset of DC, FC, PTPX, Power Compiler, Primetime, Modeltech, VCS, power theatre.
- Experience with design rule check (Spyglass), Formal verification (Formality, LEC), and/or Power analysis and simulation.
- Scripting skills (Python, PERL, TCL, or C).
- Knowledge of bus interface protocols (APB, AHB, AXI).
- Experience with post-silicon debug.
- Experience with UVM.
- C coding.
Skills: Low Power AI, AI IP blocks, Verilog RTL, power optimization, ASIC hardware design
This role has been open 3 days — well below the 65-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
518
|
Median days open
65 d
|
Median salary
$229k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (518 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 106 | 518 |
| Open roles in the wider Software, Firmware & Systems family | 722 | 5796 · 143 employers |
| Median days open | 97 d | 65 d (+32 d vs this employer) |
| Median salary (USD postings) | — | $229k |
Skills observed across this category: Low Power AI, AI IP blocks, Verilog RTL, power optimization, ASIC hardware design
Who's hiring in this category
- Qualcomm (this employer) · 106 open roles · median 97 d
- NVIDIA · 85 open roles · median 65 d
- AMD · 43 open roles · median 60 d
- Micron Technology · 32 open roles · median 37 d
- Mobileye · 25 open roles · median 51 d
- Analog Devices · 14 open roles · median 22 d
How we counted: 518 open AI/ML Hardware Engineering (AI ML Hardware) roles from 76 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.