Senior ASIC Design Engineer - DSP/Analog/SerDes - San Jose, CA, United States
$150,000 - $250,000 USD yearly
Originally posted 21 October 2026 by the employer.
Design high-speed optical communication ASICs spanning DSP, SerDes, and mixed-signal interfaces.
About the role
Celero is seeking an ASIC Design Engineer to develop ASICs for high-speed optical communication systems. The role combines digital ASIC design with hands-on work in DSP, Analog, and SerDes technologies.
What you'll do
- Design and implement digital circuits and ASIC blocks using Verilog and SystemVerilog. - Develop and integrate DSP, digital communication, and high-speed SerDes functionality into mixed-signal ASIC designs. - Design high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems. - Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and signoff activities. - Optimize designs for performance, power, and area (PPA), performing RTL simulation and debugging. - Contribute to block-level and top-level integration, verification, silicon bring-up, and automation using Python and Tcl.
What you'll need
- Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field. - 10+ years of experience in digital ASIC design with ownership of complex ASIC blocks or subsystems. - Strong proficiency in Verilog and/or SystemVerilog, with deep knowledge of RTL design and ASIC development methodologies. - Working knowledge in one or more areas: Digital Signal Processing (DSP), high-speed SerDes, Analog/Mixed-Signal ICs, digital communications, or optical communications. - Hands-on experience with DSP algorithms, data-path architectures, FEC, equalization, or modulation/demodulation. - Experience with synthesis, static timing analysis, Lint, CDC, formal verification, RTL simulation, and low-power design techniques.
Nice to have
- Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking. - Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery. - Experience with SerDes architectures including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry. - Experience with MATLAB, Python, Tcl, or other modeling and automation tools. - Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.
Skills: Verilog, DSP, SerDes, ASIC, MATLAB
This role has been open 0 days — well below the 100-day median for Digital/RTL Design roles.
Digital/RTL Design · Mixed Signal DSP
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Open roles in category
29
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Median days open
100 d
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Median salary
—
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (29 roles · 17 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 29 |
| Open roles in the wider Digital Design & Verification family | 8 | 3283 · 116 employers |
| Median days open | 0 d | 100 d (−100 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: Verilog, DSP, SerDes, ASIC, MATLAB
Who's hiring in this category
- Infineon Technologies · 4 open roles · median 45 d
- Keysight Technologies · 4 open roles · median 113 d
- Altera · 2 open roles · median 31 d
- Celero (this employer) · 2 open roles · median 127 d
- Marvell Technology · 2 open roles · median 151 d
- NXP Semiconductors · 2 open roles · median 120 d
How we counted: 29 open Digital/RTL Design (Mixed Signal DSP) roles from 17 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.