Senior ASIC Design Engineer - DSP/Analog/SerDes - Irvine, CA, United States
$150,000 - $250,000 USD yearly
Originally posted 21 October 2026 by the employer.
About the role
Celero is seeking a Senior ASIC Design Engineer to develop digital and mixed-signal ASICs for high-speed optical communication systems. The role combines digital ASIC design with hands-on integration of DSP, analog, and SerDes technologies.
What you'll do
- Design and implement digital circuits and ASIC blocks using Verilog and SystemVerilog. - Develop and integrate DSP, digital communication, and high-speed SerDes functionality into mixed-signal ASIC designs. - Participate in the design of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems. - Perform synthesis, static timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related implementation and signoff activities. - Optimize designs for performance, power, and area (PPA) and perform RTL simulation and debugging. - Contribute to block-level and top-level integration, verification, and silicon bring-up.
What you'll need
- Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field. - 10+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems. - Proficiency in Verilog and/or SystemVerilog, with strong knowledge of RTL design and ASIC development methodologies. - Strong knowledge in one or more areas: Digital Signal Processing (DSP), high-speed SerDes, Analog/Mixed-Signal ICs, digital communications, or optical communications. - Hands-on experience with synthesis, static timing analysis, lint, CDC, formal verification, and RTL simulation tools. - Experience with low-power design techniques, PPA optimization, and familiarity with verification methodologies such as UVM.
Nice to have
- Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking. - Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery. - Experience with SerDes architectures including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry. - Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up. - Experience with MATLAB, Python, Tcl, or other modeling and automation tools. - Understanding of optical communication standards and high-speed networking protocols.
Skills: Verilog, SystemVerilog, DSP, SerDes, ASIC
This role has been open 0 days — well below the 100-day median for Digital/RTL Design roles.
Digital/RTL Design · Mixed Signal DSP
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Open roles in category
29
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Median days open
100 d
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Median salary
—
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (29 roles · 17 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 29 |
| Open roles in the wider Digital Design & Verification family | 8 | 3283 · 116 employers |
| Median days open | 0 d | 100 d (−100 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: Verilog, SystemVerilog, DSP, SerDes, ASIC
Who's hiring in this category
- Infineon Technologies · 4 open roles · median 45 d
- Keysight Technologies · 4 open roles · median 113 d
- Altera · 2 open roles · median 31 d
- Celero (this employer) · 2 open roles · median 127 d
- Marvell Technology · 2 open roles · median 151 d
- NXP Semiconductors · 2 open roles · median 120 d
How we counted: 29 open Digital/RTL Design (Mixed Signal DSP) roles from 17 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.