Senior ASIC Design Engineer - DFT - CA, Santa Clara, United States
$168,000 - $310,500 USD yearly
Originally posted 10 July 2026 by the employer.
About the role
As a member of the DFX Methodology Team, you will focus on the architecture, design, implementation, and verification of DFT IPs across the full silicon lifecycle. The scope includes owning fuse controller architecture and DFT IPs for complex SoC products.
What you'll do
- Own the architecture and design of fuse controller and other DFT IPs for SoC designs. - Develop, deploy, and enhance DFT methodologies for scalability and future product needs. - Define and align feature sets by collaborating with architects, platform, and software teams. - Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration. - Create and execute test plans to support functional and DFT full-chip verification. - Support post-silicon bring-up and validation efforts, including debug, issue resolution, and mentoring junior engineers.
What you'll need
- Bachelor's degree (or equivalent experience) with 8+ years of experience, or Master's degree in Electrical Engineering or related field with 6+ years of experience. - 5+ years of hands-on experience in SoC architecture, RTL design, and verification. - Micro-architecture and RTL development experience using Verilog. - Expertise in DFT design, methodology, and implementation. - Familiarity with clocking, STA, place & route, and power optimization. - Experience in post-silicon bring-up on ATE, including pattern formats, test program development, and failure analysis. - Proficiency in scripting languages such as Python, Perl, or Tcl.
Nice to have
- UVM experience.
Skills: DFT methodologies, SoC architecture, RTL design, Verilog, post-silicon bring-up, ATPG
This role has been open 102 days — well above the 61-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
61 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 248 |
| Open roles in the wider Digital Design & Verification family | 229 | 3244 · 116 employers |
| Median days open | 30 d | 61 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: DFT methodologies, SoC architecture, RTL design, Verilog, post-silicon bring-up, ATPG
Who's hiring in this category
- AMD · 41 open roles · median 42 d
- NVIDIA (this employer) · 24 open roles · median 30 d
- Qualcomm · 23 open roles · median 104 d
- NXP Semiconductors · 19 open roles · median 44 d
- Synopsys · 14 open roles · median 28 d
- Intel Corporation · 10 open roles · median 61 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.