Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)
$192,300 - $307,600 USD yearly
Originally posted 11 August 2026 by the employer.
About the role
The successful candidate may serve as the ASIC Chip Lead, owning technical execution, or as the Project Lead, owning overall program execution, or both.
What you'll do
- Accountable for successful ASIC execution from concept through production, including schedule, quality, cost, tapeout readiness, and first-pass silicon success.
- Lead cross-functional teams including architecture, analog design, digital design, verification, physical design, package engineering, test, characterization, and operations.
- Partner with system architects and engineering leaders to define ASIC architecture, technical tradeoffs, execution strategy, and product requirements.
- Drive schedule development, critical-path management, milestone tracking, and risk mitigation.
- Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners.
- Drive tapeout readiness reviews and silicon bring-up planning.
What you'll need
- BSEE, MSEE, or equivalent with 15+ years of semiconductor industry experience and 5+ years leading complex ASIC developments.
- Demonstrated success leading multiple complex mixed-signal ASICs through architecture, design, verification, tapeout, silicon bring-up, and production.
- Experience managing geographically distributed teams and external design partners.
- Strong program management skills, including schedule planning, risk management, and executive communications.
- Proven ability to lead through influence across multiple engineering disciplines.
Nice to have
- Experience with advanced-node ASIC development.
Skills: ASIC, mixed-signal, tapeout, silicon bring-up, ATE
This role has been open 66 days — well above the 46-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
175
|
Median days open
46 d
|
Median salary
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (175 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 175 |
| Median days open | 66 d | 46 d (+20 d vs this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: ASIC, mixed-signal, tapeout, silicon bring-up, ATE
Who's hiring in this category
- Qualcomm · 25 open roles · median 46 d
- NVIDIA · 20 open roles · median 34 d
- AMD · 19 open roles · median 25 d
- Synopsys · 14 open roles · median 46 d
- Arm Holdings · 10 open roles · median 83 d
- Astera Labs · 6 open roles · median 67 d
How we counted: 175 open Technical Program Management (SOC Architecture) roles from 49 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.