$126,700 - $190,100 USD yearly
Originally posted 28 October 2026 by the employer.
About the role
This role drives functional, performance, and power enhancements into hardware accelerators to enable AI training capabilities across end devices, data centers, and systems.
What you'll do
- Architect enhancements required for efficient training of AI models, including flexible computational blocks supporting dense and sparse GEMM and GEMV across multiple datatypes and precisions.
- Define architecture for memory subsystems, scale-out, and scale-up topologies including switches, Network-on-Chip (NoC), and codesign with communication collectives.
- Codesign hardware with software and GenAI (LLM) requirements while evaluating performance, area, and power trade-offs including memory and bus impacts.
- Develop performance models to validate architecture proposals and provide pre-silicon performance predictions for ML training workloads.
- Conduct competitive analysis and evaluate current accelerator and GPU architectures against hardware requirements for AI training systems.
What you'll need
- Bachelor's degree in Computer Science, Engineering, Information Systems, or a related field with 2+ years of relevant engineering experience (or Master's with 1+ year, or PhD).
- 3 years of hardware engineering experience defining the architecture of GPUs or accelerators used for training AI models.
- In-depth knowledge of NVIDIA or AMD GPU capabilities and architectures.
- Knowledge of LLM architectures and their hardware requirements.
Nice to have
- Knowledge of computer architecture, digital circuits, and hardware simulators, with high-level hardware modeling experience.
- Experience in modeling hardware and workloads to extract performance and power estimates.
- Knowledge of Network-on-Chip (NoC) designs, communication protocols, and memory technologies used in AI systems.
- Familiarity with AI training systems such as NVIDIA DGX and NVL72, as well as distributed training frameworks such as DeepSpeed and FSDP.
- Experience with front-end ML frameworks (TensorFlow, PyTorch), ML model classes (CNN, RNN), and coding in C and Python.
Skills: AI architecture, GEMM, performance modeling, accelerator, LLM
More semiconductor jobs: Qualcomm jobs · AI chip design jobs · San Diego jobs
First seen in our index 15 days ago, well below the 108-day median for AI/ML Hardware Engineering roles.
AI/ML Hardware Engineering · AI ML Hardware
|
Open roles in category
479
|
Median days since first seen
108 d
|
Category median salary (all employers)
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (479 roles · 73 employers) |
|---|---|---|
| Open roles in this specialty | 101 | 479 |
| Open roles in the wider Software, Firmware & Systems family | 738 | 6700 · 161 employers |
| Median days since first seen | 124 d | 108 d (−16 d vs this employer) |
| Median salary (USD postings) | n/a | $238k |
Skills observed across this category: AI architecture, GEMM, performance modeling, accelerator, LLM
Who's hiring in this category
- NVIDIA · 109 open roles · median 87 d
- Qualcomm (this employer) · 100 open roles · median 125 d
- AMD · 21 open roles · median 127 d
- Mobileye · 15 open roles · median 101 d
- Analog Devices · 14 open roles · median 50 d
- Micron Technology · 14 open roles · median 65 d
How we counted: 479 open AI/ML Hardware Engineering (AI ML Hardware) roles from 73 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Software, Firmware & Systems family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.