Senior AE, SerDes Design IP - San Jose, United States
$123,200 - $228,800 USD yearly
Originally posted 5 August 2026 by the employer.
Provide technical pre-sales support for Cadence SerDes, PCIe, CXL, and Ethernet PHY and controller design IP.
About the role
As a Senior Applications Engineer, you will provide technical pre-sales support to win design IP business using knowledge of high-speed interface standards such as PCIe, CXL, Ethernet, and USB. The role focuses on Cadence's serial interface PHY and controller IP portfolio used in data centers, mobile devices, automobiles, and consumer devices.
What you'll do
- Provide technical pre-sales support for High-Speed Interface IP, including PCIe, CXL, and Ethernet PHY and Controllers. - Present Cadence’s IP portfolio and capabilities to prospective customers and deliver IP performance demos at industry events. - Work closely with IP Sales staff, marketing, and R&D teams to win business opportunities. - Deliver quick-turn product-specific technical support to customers, field teams, architects, and designers. - Write application notes and articles for internal and external publication. - Travel occasionally to customer sites.
What you'll need
- BS in EE, CE, or related equivalent with 2+ years of relevant work experience, or an MS in EE, CE, or equivalent. - Technical knowledge of high-speed interface standards including PCIe, CXL, Ethernet, and USB. - Demonstrated initiative to manage pre-sales accounts. - Presentation skills and verbal/written communication skills for customer-facing technical interactions.
Nice to have
- Experience on high-speed interface controller and/or PHY design/verification. - Working knowledge of high-speed interface PHY. - Knowledge of one or more high speed interface protocols: PCIe, CXL, UCIe, Ethernet, USB, MIPI, 112G, or 56G. - Lab validation or demo setup experience.
Skills: high-speed interface standards, PCIe, CXL, Serdes IP, customer facing
This role has been open 106 days — well above the 57-day median for Applications FAE roles.
Applications FAE · Serdes Highspeed
|
Open roles in category
89
|
Median days open
57 d
|
Median salary
$183k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (89 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 89 |
| Median days open | 26 d | 57 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Skills observed across this category: high-speed interface standards, PCIe, CXL, Serdes IP, customer facing
Who's hiring in this category
- Astera Labs · 16 open roles · median 67 d
- Synopsys · 16 open roles · median 35 d
- Keysight Technologies · 10 open roles · median 46 d
- Qualcomm · 8 open roles · median 73 d
- Microchip Technology · 7 open roles · median 41 d
- Marvell Technology · 5 open roles · median 179 d
How we counted: 89 open Applications FAE (Serdes Highspeed) roles from 23 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.