Semicustom DFT Strategy Lead - TX, Austin, United States
Originally posted 28 May 2026 by the employer.
About the role
The Semicustom DFT Strategy Lead defines and drives company-wide DFT roadmap strategy and alignment across Design, Product Engineering, and Quality functions. The role is part of Central DFX (CDFX), supporting complex APU computing, game console, and GPU graphics products.
What you'll do
- Work closely with SOC and PDG teams to drive adoption of and ensure compliance with the company-wide DFT strategy. - Advocate for maintaining testability features throughout design stages, including floor planning and timing closure. - Follow up with post-silicon experiments to analyze the effectiveness and return on investment of DFT features. - Influence and collaborate with outside partners across the EDA and ATE industries. - Evaluate external tools to drive build-versus-buy decisions, leading teams to architect, implement, deploy, and maintain internal solutions when built.
What you'll need
- Extensive experience across DFT and semiconductor testing methodologies. - Proven experience evaluating and utilizing EDA and ATE tools. - Experience with post-silicon experiments and analyzing test effectiveness and DPPM metrics. - Track record collaborating with SOC, PDG, and product teams across floor planning and timing closure stages. - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Nice to have
- Experience defining a comprehensive DFT roadmap strategy across an enterprise design organization. - Experience developing, architecting, and deploying internal DFT CAD tools. - Demonstrated experience partnering directly with external EDA and ATE vendors.
Skills: DFT, testability, design-for-test, ATPG, post-silicon experiments
This role has been open 148 days — well above the 63-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
63 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 248 |
| Open roles in the wider Digital Design & Verification family | 251 | 3328 · 115 employers |
| Median days open | 45 d | 63 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DFT, testability, design-for-test, ATPG, post-silicon experiments
Who's hiring in this category
- AMD (this employer) · 38 open roles · median 45 d
- Qualcomm · 26 open roles · median 73 d
- NVIDIA · 23 open roles · median 42 d
- NXP Semiconductors · 19 open roles · median 47 d
- Synopsys · 15 open roles · median 30 d
- Intel Corporation · 11 open roles · median 53 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.