Semiconductor Packaging Integration Research Manager - United States

Originally posted 11 September 2026 by the employer — open 8 days.

About the role

What you'll do

• Lead packaging integration research programs focused on heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging, and emerging die-to-die interconnect technologies.
• Define integration research strategy, technical roadmaps, research milestones, and decision criteria aligned to future product, platform, and system-level scaling requirements.
• Manage multidisciplinary team of integration researchers, packaging technologists, process integration engineers, modeling experts, design, and technical program leads.
• Translate system requirements into package integration solutions by balancing performance, power, area, latency, bandwidth, thermal behavior, mechanical stress, reliability, cost, and manufacturability.
• Drive feasibility studies, architecture trade-off analysis, process module evaluation, design rule development, prototyping, design-of-experiments, and experimental validation for new integration concepts.
• Lead technology readiness assessments, integration risk reviews, failure analysis learning cycles, reliability evaluations, and manufacturing feasibility reviews for early-stage packaging options.

What you'll need

• Demonstrated experience leading advanced technology research programs, multidisciplinary technical teams, cross-functional initiatives, or external research collaborations.
• Ability to convert ambiguous integration challenges into clear hypotheses, experimental plans, measurable milestones, technology readiness criteria, and actionable recommendations.
• Strong understanding of package-system integration, chiplet architectures, advanced interconnects, substrates, interposers, assembly materials, wafer-level processes, thermal-mechanical behavior, power delivery, signal integrity, reliability, and manufacturability trade-offs.
• Strong communication skills with the ability to present complex technical findings, integration trade-offs, risks, and recommendations to executive, technical, and cross-functional audiences.
• Master’s degree in electrical engineering, Mechanical Engineering, Materials Science, Chemical Engineering, Applied Physics, Microelectronics, Semiconductor Manufacturing, or a related engineering or science discipline.
• Minimum of 7 years of experience in semiconductor technology roles, preferably packaging integration, advanced packaging research, heterogeneous integration, process integration, or package development.

Nice to have

• Strong record of innovation in semiconductor packaging integration, heterogeneous integration, chiplet architectures, 2.5D/3DIC, hybrid bonding, interposer technology, fan-out, wafer-level packaging, substrate technology, or package-system co-optimization.
• Experience with research-to-development transfer, technology readiness frameworks, pathfinding, prototype builds, process integration learning, and early manufacturing feasibility assessment.
• Knowledge of thermal-mechanical modeling, warpage, stress, CTE mismatch, electromigration, reliability physics, high-speed I/O, power integrity, signal integrity, die-to-die interfaces, and package-level co-design.
• Demonstrated record of patents, publications, conference presentations, industry consortia participation, university research collaboration, or external ecosystem leadership.
• Experience leading multi-organization collaborations with suppliers, equipment vendors, universities, research labs, OSATs, foundry partners, design teams, or customer technology teams.
• Familiarity with AI, HPC, data center, automotive, mobile, networking, edge computing, advanced memory, or custom silicon packaging requirements.

Skills: heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging