$151,000 USD yearly
Work on root of trust architectures, TPM integration, and secure boot across QEMU, HAPS, and HTG FPGA emulation environments.
Originally posted 30 October 2026 by the employer.
About the role
As a Security Lead at Axiado, you will oversee information security testing, develop security control test plans, and investigate vulnerabilities across complex SoC platforms. The work centers on root of trust architectures, secure boot, and TPM-integrated data protection using NIST-approved cryptographic algorithms across QEMU and FPGA emulation environments.
What you'll do
- Assess the effectiveness of information security controls using defined performance indicators, overseeing security testing across QEMU, HAPS, and HTG FPGA emulation environments.
- Design and implement TPM-integrated data protection and encryption solutions using NIST-approved algorithms, including ECDSA, SHA, and AES.
- Architect secure boot and root of trust mechanisms to establish a hardware-anchored chain of trust from power-on through OS and application layers.
- Investigate information security breaches, analyze vulnerabilities, and troubleshoot security issues on complex SoC platforms using Lauterbach TRACE32 and SEGGER J-Link debuggers over JTAG interfaces.
- Develop and maintain information security policies, standards, and control test plans aligned with applicable cybersecurity standards and regulations.
- Investigate and document security incidents, review internal and external security assessments, and recommend mitigations to reduce information security risk.
What you'll need
- Master's degree (or foreign equivalent) in Electrical Engineering, Computer Engineering, or a closely related field.
- At least 1 year of experience in a related role, such as Security Lead, Embedded Security Engineer, Computer Programmer, or Test Engineer.
- At least 1 year of hands-on experience with Secure Boot and Root of Trust (RoT).
- At least 1 year of hands-on experience with Trusted Platform Module (TPM).
- At least 1 year of experience implementing ECDSA, SHA, and AES cryptographic algorithms.
- At least 1 year of experience working with QEMU, HAPS, and HTG FPGA emulators.
- At least 1 year of experience using Lauterbach TRACE32 and SEGGER J-Link debuggers over JTAG interfaces.
Skills: Secure Boot, Root of Trust, TPM, ECDSA, AES, SoC
First seen in our index 0 days ago, well below the 62-day median for Hardware Security Engineering roles.
Hardware Security Engineering · Hardware Security
|
Open roles in category
174
|
Median days since first seen
62 d
|
Category median salary (all employers)
$221k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Axiado | All employers we track in this specialty (174 roles · 41 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 174 |
| Median days since first seen | 0 d | 62 d (+62 d vs this employer) |
| Median salary (USD postings) | n/a | $221k |
Skills observed across this category: Secure Boot, Root of Trust, TPM, ECDSA, AES, SoC
Who's hiring in this category
- NVIDIA · 33 open roles · median 57 d
- NXP Semiconductors · 22 open roles · median 123 d
- Qualcomm · 17 open roles · median 97 d
- Arm Holdings · 13 open roles · median 98 d
- AMD · 8 open roles · median 83 d
- Synopsys · 8 open roles · median 28 d
How we counted: 174 open Hardware Security Engineering (Hardware Security) roles from 41 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Days are counted from when our index first saw each posting, not from the employer's original posting date.