RTL2GDS IC Sr. Principal Design Engineer - San Jose, United States
$161,000 - $299,000 USD yearly
Originally posted 9 September 2026 by the employer.
This role focuses on solving Digital Implementation problems using Cadence technology.
About the role
This role involves driving pre-sales and post-sales activities for Cadence Digital IC products at advanced nodes, focusing on Digital Implementation and Signoff.
What you'll do
- Provide technical support to Cadence customers for Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff.
- Guide customers on utilizing Cadence technologies to achieve design goals and meet project schedules.
- Conduct technical presentations and product demonstrations and drive technical evaluations/benchmarks to success.
- Work with R&D to enhance tools and methodologies to meet customer requirements.
- Drive adoption and proliferation of Cadence tools and technologies.
- Amend and augment design flows using Tcl and/or other programming skills.
What you'll need
- BS, MS, or PhD in EE with 10-12 years of industry experience in design and EDA (Digital Implementation/Signoff).
- Understanding of ASIC Design implementation process and steps.
- Strong hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler).
- Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler).
- Experience with EDA tools in IC digital implementation & signoff flows (STA tools).
- Strong STA and SDC debugging abilities.
- Automation skills using Perl, Tcl, and shell scripting.
- Strong analytical & analysis skills covering digital implementation.
Nice to have
- Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience.
Skills: Digital Implementation, Synthesis, Place and Route, Signoff, Cadence
This role has been open 36 days — well below the 78-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
688
|
Median days open
78 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (688 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 155 | 688 |
| Open roles in the wider Physical Implementation family | 178 | 1469 · 108 employers |
| Median days open | 168 d | 78 d (+90 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: Digital Implementation, Synthesis, Place and Route, Signoff, Cadence
Who's hiring in this category
- Cadence Design Systems (this employer) · 153 open roles · median 168 d
- Synopsys · 65 open roles · median 38 d
- Micron Technology · 44 open roles · median 80 d
- Qualcomm · 41 open roles · median 66 d
- NVIDIA · 39 open roles · median 79 d
- GlobalFoundries · 33 open roles · median 35 d
How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.