RTL Tools & Methodology Engineer - CA, San Jose, United States
Originally posted 28 April 2026 by the employer. Relisted by the employer on 2 May 2026.
RTL tools and static verification methodology role focused on FPGA development.
About the role
AMD is seeking an RTL Tools & Methodology Engineer to help define, deploy, and improve front-end design and static verification flows. This role focuses on supporting tooling and methodologies for FPGA development across the engineering organization.
What you'll do
- Collaborate with the design team to support front-end design methodologies, focusing on Lint, CDC, formal equivalence, and low-power verification. - Deploy and improve static verification tools and methodology ecosystems across RTL design workflows. - Partner with RTL designers and verification engineers to ensure high-quality front-end design flows. - Leverage corporate AI systems to increase engineering productivity and streamline workflows.
What you'll need
- Bachelor's degree in Electrical or Computer Engineering. - Experience or background in RTL design and logic design. - Hands-on experience with static verification using SystemVerilog, Verilog, or VHDL. - Scripting and programming proficiency in Perl, Python, and TCL.
Nice to have
- Master's or PhD degree in Electrical or Computer Engineering.
Skills: RTL design, static verification, Perl, Python, TCL, FPGA
This role has been open 180 days — well above the 71-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
694
|
Median days open
71 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (694 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 694 |
| Open roles in the wider Physical Implementation family | 89 | 1513 · 111 employers |
| Median days open | 27 d | 71 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: RTL design, static verification, Perl, Python, TCL, FPGA
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 153 d
- Synopsys · 62 open roles · median 44 d
- Micron Technology · 44 open roles · median 53 d
- GlobalFoundries · 39 open roles · median 27 d
- Qualcomm · 39 open roles · median 77 d
- Keysight Technologies · 34 open roles · median 80 d
How we counted: 694 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.