Originally posted 6 August 2026 by the employer.
About the role
Mueon is hiring an RTL-to-GDS Design Engineer to implement digital IP and SoC subsystems from synthesis through final GDSII release.
What you'll do
- Implement digital IP blocks and SoC subsystems from RTL through GDSII, including synthesis, floorplanning, placement, clock tree synthesis, routing, and physical implementation.
- Perform static timing analysis and drive timing closure across multiple operating modes and process corners.
- Debug and resolve setup, hold, congestion, signal integrity, and physical implementation issues to achieve design closure.
- Develop and maintain implementation scripts, automation, and methodologies using Tcl, Python, Perl, or similar scripting languages.
- Coordinate with physical verification teams to resolve DRC, LVS, antenna, and engineering change order (ECO) issues.
- Support DFT implementation, power analysis, low-power design techniques, and final tapeout activities through GDSII release.
What you'll need
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience.
- 3-6 years of experience in RTL-to-GDS implementation for ASIC or SoC designs.
- Experience with synthesis, floorplanning, placement, clock tree synthesis, routing, and physical implementation using industry-standard EDA tools.
- Experience with static timing analysis and multi-corner, multi-mode timing closure.
- Familiarity with physical verification methodologies including DRC, LVS, and signoff flows.
- Understanding of low-power implementation techniques and power analysis methodologies.
Nice to have
- Experience with advanced semiconductor process technologies (16 nm and below).
- Experience implementing AI accelerators, CPUs, GPUs, networking ASICs, or other high-performance digital designs.
- Experience integrating DFT features including scan, BIST, and ATPG into physical implementation flows.
- Familiarity with formal equivalence checking, EM/IR analysis, and advanced signoff methodologies.
- Experience with memory subsystems, embedded SRAM, or high-bandwidth memory integration.
- Experience supporting production tapeouts and silicon bring-up.
More semiconductor jobs: RTL design jobs · Hillsboro jobs
First seen in our index 0 days ago, well below the 65-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1098
|
Median days since first seen
65 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Mueon | All employers we track in this specialty (1098 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 1098 |
| Open roles in the wider Digital Design & Verification family | 8 | 3506 · 120 employers |
| Median days since first seen | 0 d | 65 d (+65 d vs this employer) |
| Median salary (USD postings) | n/a | $188k |
Who's hiring in this category
- Qualcomm · 142 open roles · median 74 d
- AMD · 92 open roles · median 55 d
- Synopsys · 89 open roles · median 54 d
- NVIDIA · 48 open roles · median 67 d
- NXP Semiconductors · 45 open roles · median 110 d
- Analog Devices · 40 open roles · median 57 d
How we counted: 1098 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.