RTL Power Engineer - Santa Clara, CA, United States
$200,000 - $350,000 USD yearly
Originally posted 19 August 2026 by the employer.
Design power management for the Physical AI SoC.
About the role
This role involves owning power management of the SoC at every level, delivering silicon that meets performance targets within power budgets.
What you'll do
- Design on-chip power management hardware including digital power meters, activity monitors, and throttlers. - Design hardware and software control loops around temperature sensors to maintain thermal limits. - Design controls for activity, average power, and instantaneous di/dt limits. - Collaborate with architects, physical design, and package teams on voltage droop behavior, power delivery, and adaptive clocking. - Own clock and reset architecture, including clock gating, PLL programming, and reset sequencing across power domains. - Define and implement power state management, including DVFS, power domains, retention, and low power flows. - Correlate power estimates across RTL, emulation, and silicon, building telemetry for power and thermal behavior. - Work with firmware and software teams on interfaces, policies, and telemetry for power and thermal management.
What you'll need
- Strong grasp of physics and electrical engineering behind average power, peak current, thermal behavior, and voltage droop. - Experience designing power management hardware such as digital power meters, throttlers, or thermal and current control loops. - Understanding of di/dt, IR drop, power delivery network behavior, and their impact on timing margin. - Experience with clock and reset architecture including clock gating, PLL management, and reset sequencing. - Working knowledge of Verilog or SystemVerilog and modern RTL design methodology. - Experience with power estimation and analysis flows from RTL through gate level. - Strong debugging and problem solving skills across hardware and software boundaries. - BS or higher in Electrical Engineering, Computer Engineering or a related field.
Nice to have
- Experience with DVFS, adaptive voltage scaling, adaptive clocking, or droop detection. - Experience with UPF based low power design including power domains, retention, and isolation. - Experience correlating pre silicon power models against silicon measurement. - Experience with thermal modeling, sensor placement, or package and board level thermal design. - Experience with firmware or PMIC interfaces and power management software. - Experience with power analysis tools such as PowerArtist, PrimePower or Joules. - Familiarity with robotics, drones, autonomous vehicles, or edge AI systems. - Experience using AI assisted design workflows.
This role has been open 57 days — below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 1021 |
| Open roles in the wider Digital Design & Verification family | 17 | 3198 · 115 employers |
| Median days open | 82 d | 62 d (+20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 140 open roles · median 62 d
- Synopsys · 85 open roles · median 30 d
- AMD · 71 open roles · median 36 d
- Analog Devices · 48 open roles · median 50 d
- NVIDIA · 46 open roles · median 64 d
- NXP Semiconductors · 41 open roles · median 85 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.