RTL Methodology Silicon Design Engineer - TX, Austin, United States
Digital Design & SoC Architecture
Originally posted 15 October 2026 by the employer.
About the role
What you'll do
- Execute and refine the methodology and tools for RTL design work
- Own and advance the RTL static analysis ecosystem, including linting flows, rule authoring, waiver management, SystemVerilog/Verilog parsers, ASTs, and custom code-analysis tooling
- Identify high-value opportunities to apply AI across the RTL design flow and drive prototypes into production use
- Collaborate with hardware and infrastructure engineers to develop best-in-class engineering infrastructure for RTL development
- Contribute to silicon debug and product support as needed
What you'll need
- Experience with Verilog/SystemVerilog RTL development within CPU, SoC, ASIC, or digital-design environments
- Experience with RTL linting, static analysis, design methodology, and code-quality tooling
- Experience with HDL parsers, ASTs, or source-code analysis and transformation tools such as Verible, Slang, Verilator, Surelog, or comparable technologies
- Experience building applications or engineering tools using large language models, including RAG, agentic frameworks, tool/function calling, or prompt engineering
- Experience applying AI coding assistants or agents within engineering-development workflows
- Proficiency with scripting languages such as Python, Perl, Ruby, Shell, and/or TCL
- Programming experience with Python, Go, Java, C#, TypeScript, or comparable languages
- Familiarity with digital-design workflows including synthesis, verification, physical design, place and route, and timing closure
Market context
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 71 | 1021 |
| Open roles in the wider Digital Design & Verification family | 253 | 3198 · 115 employers |
| Median days open | 36 d | 62 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 140 open roles · median 62 d
- Synopsys · 85 open roles · median 30 d
- AMD (this employer) · 71 open roles · median 36 d
- Analog Devices · 48 open roles · median 50 d
- NVIDIA · 46 open roles · median 64 d
- NXP Semiconductors · 41 open roles · median 85 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.