RTL Designer - Santa Clara, CA, United States
$125,000 - $500,000 USD yearly
Originally posted 15 July 2026 by the employer.
Velaura AI is building a Physical AI SoC.
About the role
As an RTL Designer, you will contribute to the design of Velaura AI's Physical AI SoC, transforming architectural concepts into production silicon.
What you'll do
- Design, implement, and optimize RTL for key portions of the Velaura AI SoC.
- Collaborate with architects to develop robust and efficient microarchitectures.
- Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
- Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and power-management logic.
- Optimize designs for performance, power, area, scalability, and reliability.
- Analyze performance bottlenecks and propose architectural and implementation improvements.
What you'll need
- Experience designing RTL for complex digital systems.
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
- Experience with Verilog/SystemVerilog and modern RTL design methodologies.
- Familiarity with performance, power, and area tradeoffs.
- Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.
- Experience with hardware/software co-design and system-level performance optimization.
- Strong debugging and problem-solving skills.
Nice to have
- Experience with AI, machine learning, or edge AI hardware.
- Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
- Knowledge of low-power design techniques and power management architectures.
- Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.
- Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and advanced driver-assistance systems (ADAS), aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.
This role has been open 84 days — well above the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1036
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (1036 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 1036 |
| Open roles in the wider Digital Design & Verification family | 26 | 3201 · 115 employers |
| Median days open | 45 d | 61 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 140 open roles · median 65 d
- Synopsys · 86 open roles · median 33 d
- AMD · 71 open roles · median 39 d
- Analog Devices · 47 open roles · median 51 d
- NVIDIA · 42 open roles · median 61 d
- NXP Semiconductors · 42 open roles · median 87 d
How we counted: 1036 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.