RTL Design Manager - CA, San Jose, United States
Originally posted 7 July 2026 by the employer. Relisted by the employer on 24 September 2026.
Lead front-end RTL design and SoC integration within the AECG IP & SOC group.
About the role
As an RTL Design Manager for the AECG IP & SOC group, you will manage front-end design and integration while working closely with architecture, IP design, physical design, and product engineering teams.
What you'll do
- Lead an engineering team focused on front-end RTL development. - Own the design and implementation of blocks to meet functional, timing, area, and power requirements. - Guide and review functional verification for assigned design blocks. - Design and implement logic functions that enable efficient test and debug. - Implement automation to increase design team efficiency.
What you'll need
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. - Strong front-end RTL engineering background. - Experience owning block-level design and implementation through functional, timing, area, and power closure. - Demonstrated technical leadership capabilities guiding team deliverables and reviews.
Nice to have
- Experience with Arm architecture and APB, AXI, and CHI protocols. - Experience with design reuse, including RTL, constraints, and waivers. - Experience with SoC-level design integration. - Experience with automation using scripting techniques such as Perl, Python, or Tcl. - Experience with timing constraints and timing exceptions. - Experience running standard quality checks such as LINT and CDC. - Experience designing with multiple power domains including writing UPF.
This role has been open 106 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1051
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1051 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 76 | 1051 |
| Open roles in the wider Digital Design & Verification family | 254 | 3283 · 116 employers |
| Median days open | 40 d | 62 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 150 open roles · median 57 d
- Synopsys · 84 open roles · median 35 d
- AMD (this employer) · 72 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 89 d
- NVIDIA · 40 open roles · median 62 d
How we counted: 1051 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.