RTL Design Lead/IC Front-End Architect/Datapath Lead - San Jose, United States
Originally posted 24 June 2026 by the employer.
Lumilens is building critical photonics infrastructure for AI supercomputing.
About the role
You will define the digital front-end micro-architecture and personally own the high-speed datapath that moves data between UCIe and the optical front end for a first-of-its-kind chiplet.
What you'll do
- Define front-end micro-architecture and block partitioning. - Establish front-end design methodology and quality, including RTL coding standards, lint, CDC/RDC signoff, and clean-RTL policy. - Own the high-speed datapath, including per-lane alignment/deskew/mux, UCIe streaming /RDI adapter, elastic FIFOs, and custom logic. - Architect transport/link framing/mapping and adaptation logic. - Design timing- and floorplan-aware micro-architecture, including pipelining, retiming, and partitioning for physical closure at multi-hundred-Gbps. - Establish designer-level verification, including block-level testbenches/sanity checks and assertion (SVA) coverage.
What you'll need
- 10+ years digital design / micro-architecture experience, with lead ownership of a high-throughput datapath or SerDes-adjacent SoC. - Experience designing the datapath of a network switch/NIC card or memory controller. - Understanding of interconnect architectures and their bandwidth/latency trade-offs. - Strong SystemVerilog RTL and timing-aware micro-architecture at multi-hundred-Gbps aggregate rates; CDC discipline. - Working command of UCIe/PCIe/CXL datapath concepts and high-speed lane alignment/deskew. - Proven ownership of front-end design methodology, including lint/CDC/RDC signoff, clocking/reset architecture, and design-for-test and physical-closure collaboration. - Track record translating system requirements into an implementable, verifiable architecture spec.
Nice to have
- UCIe (or PCIe/CXL/CHI) interface architecture; die-to-die / chiplet experience. - FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping. - Optical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.
This role has been open 73 days — well above the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1037
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Lumilens | All employers we track in this specialty (1037 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1037 |
| Open roles in the wider Digital Design & Verification family | 8 | 3201 · 115 employers |
| Median days open | 73 d | 60 d (+13 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 140 open roles · median 64 d
- Synopsys · 86 open roles · median 32 d
- AMD · 71 open roles · median 38 d
- Analog Devices · 47 open roles · median 50 d
- NVIDIA · 44 open roles · median 60 d
- NXP Semiconductors · 42 open roles · median 86 d
How we counted: 1037 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.