RTL Design Engineer - TX, Austin, United States
Originally posted 27 October 2026 by the employer.
About the role
As an RTL Design Engineer on AMD's Security IP (SECIP) Design team, you will contribute to block-level RTL design and subsystem-level integration for complex embedded microprocessor subsystems. The team develops embedded microprocessor subsystems and hardware accelerators supporting security policy management, cryptography, data compression, high-throughput DMA, and power management across client, server, graphics, and gaming platforms.
What you'll do
- Develop and maintain block-level RTL IP and microprocessor subsystem specifications, microarchitecture, RTL implementations, and associated design methodologies. - Design, implement, and debug RTL solutions using directed C-DPI based testing, verification team testbenches, and regression environments to achieve functional and coverage closure. - Analyze regression failures, debug simulations, evaluate coverage results, and collaborate with teams across lint, timing, DFT, DFP, and signoff requirements. - Contribute to verification planning by reviewing feature specifications, defining test plans, influencing testbench architecture, and promoting design-for-verification practices. - Debug and resolve subsystem and SoC integration issues in collaboration with SoC Integration, SoC Design Verification, emulation, and post-silicon validation teams. - Provide technical leadership in IP architecture and RTL design methodologies.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. - Experience in RTL development and subsystem-level integration targeting performance, power, and area (PPA) constraints. - Experience debugging simulations and working with functional verification environments to achieve coverage closure. - Knowledge of design signoff workflows including lint and timing.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. - Understanding of CPU and embedded microprocessor subsystem architectures, datapath-oriented accelerator microarchitectures, and FPGA-based emulation and prototyping methodologies. - Proficiency in Verilog and SystemVerilog, alongside scripting in Python, Tcl, Perl, Ruby, or Make. - Understanding of industry-standard bus and interface protocols, including AXI, AHB, and AMBA. - Experience with ASIC development tools and flows, including simulation, debug, linting, synthesis, timing analysis, and power-aware verification. - Domain-specific expertise in security, processor subsystems, or accelerators.
This role has been open 0 days — well below the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 81 | 1081 |
| Open roles in the wider Digital Design & Verification family | 259 | 3359 · 116 employers |
| Median days open | 42 d | 66 d (−24 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD (this employer) · 77 open roles · median 45 d
- Analog Devices · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.