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AMD

RTL Design Engineer – Power Design - TX, Austin, United States

AMD US, TX, Austin, United States Full-time 20 days ago
Digital Design & SoC Architecture

Originally posted 22 September 2026 by the employer.

About the role

This role involves designing and verifying embedded microprocessor subsystems and hardware accelerators critical to enhancing performance, functionality, and efficiency for System-on-Chip (SoC) products across AMD business units.

What you'll do

  • Develop and maintain RTL-level IP power specifications, aligning IP power architecture and solutions with SoC power requirements.
  • Define, track, and drive IP power targets by correlating power design intent with measurement results.
  • Collaborate with verification teams to develop power vectors for simulation-based power measurements.
  • Partner with static power measurement teams to develop and maintain power regression infrastructure, debug power-related issues, and analyze results.
  • Work with corporate power methodology and SoC power teams to adopt advanced power architecture, design, analysis, and measurement methodologies.
  • Provide technical leadership in power architecture, design, analysis, and measurement methodology development.

What you'll need

  • Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.
  • Deep knowledge of modern RTL-level power architecture, design, analysis, measurement methodologies, and industry best practices.
  • Strong understanding of microprocessor (MP) subsystem architectures, RTL microarchitectures for datapath accelerators, and low-power design methodologies.
  • Solid understanding of industry-standard on-chip bus and interface protocols, including AMBA, AXI, and AHB.
  • Experience with ASIC design and verification tools, including RTL simulation, linting, synthesis, power-aware verification, and debugging.

Nice to have

  • Proficiency in Verilog/SystemVerilog and scripting languages such as Python, Tcl, Perl, and Ruby, as well as Makefile-based development environments.
Market context

This role has been open 19 days — well below the 61-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
1017
Median days open
61 d
Median salary
$185k
See the full market breakdown ▾Category comparison, and who else is hiring
How AMD compares in Digital/RTL Design hiring
Metric AMD All employers we track in this specialty (1017 roles · 98 employers)
Open roles in this specialty 75 1017
Open roles in the wider Digital Design & Verification family 265 3171 · 114 employers
Median days open 32 d 61 d (−29 d vs this employer)
Median salary (USD postings) — $185k

Who's hiring in this category

  • Qualcomm · 138 open roles · median 61 d
  • Synopsys · 86 open roles · median 25 d
  • AMD (this employer) · 75 open roles · median 32 d
  • Analog Devices · 50 open roles · median 42 d
  • NXP Semiconductors · 48 open roles · median 79 d
  • NVIDIA · 45 open roles · median 65 d

How we counted: 1017 open Digital/RTL Design (RTL Design) roles from 98 employers tracked in the SemiconductorJobs index, counted 11 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
US, TX, Austin, United States
On-site
Full-time
20 days ago

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