RTL / Circuit IP Design Engineer - CA, San Jose, United States
Originally posted 26 June 2026 by the employer.
Implement and verify programmable embedded IP targeting custom implementations and RTL synthesis.
About the role
The focus of this role is to plan, build, and execute the implementation of new and existing features for AMD's programmable embedded IP. The final designs must meet product-defined power, performance, and area targets with intended functionality that operates on silicon and is modeled accurately for customer design use.
What you'll do
- Collaborate with architects, hardware engineers, and software engineers to understand new features to be implemented. - Author implementation documentation accounting for interactions with other features, hardware, and software modeling use cases. - Estimate the time required to implement new features, collaborate with design verification test development, and execute required changes based on cross-functional feedback. - Build directed and random verification tests. - Debug test failures to determine root causes, working with RTL and firmware engineers to resolve design defects and correct test issues. - Review functional and code coverage metrics, modifying or adding tests or constraining random tests to meet coverage requirements.
What you'll need
- Bachelors or Masters degree in Computer Engineering or Electrical Engineering. - Experience with modern processor architecture, digital design, and verification. - Experience collaborating with engineering teams across different sites and timezones.
Nice to have
- Proficiency in IP-level RTL implementation and debugging RTL code using simulation tools. - Proficiency in navigating UVM generated test results within Linux and Windows environments. - Experience with Verilog and SystemVerilog. - Strong understanding of circuit design concepts and translating circuit designs to custom implementations or RTL synthesis. - Experience automating workflows in a distributed compute environment. - Troubleshooting component designs, including timing analysis and constraint setting. - Exposure to simulation profile, efficiency improvement, acceleration, and HLS tools/processes. - Background in developing and verifying SAPR constraints. - Understanding and hands-on experience with UPF concepts. - Working knowledge of clocking, reset, and power domain crossings. - Scripting language experience in Python, Perl, Ruby, Makefile, or shell. - Experience with circuit macro generation, characterization, and collateral release processes, or exposure to high speed interfaces.
This role has been open 118 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1070
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1070 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 76 | 1070 |
| Open roles in the wider Digital Design & Verification family | 254 | 3298 · 115 employers |
| Median days open | 41 d | 62 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 153 open roles · median 58 d
- Synopsys · 87 open roles · median 35 d
- AMD (this employer) · 76 open roles · median 40 d
- Analog Devices · 49 open roles · median 51 d
- NXP Semiconductors · 42 open roles · median 90 d
- NVIDIA · 41 open roles · median 62 d
How we counted: 1070 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.