RISCV Infra System IP DV - Sr Lead Engineer - Bangalore, India
Originally posted 10 September 2026 by the employer — open 8 days.
About the role
This role involves the verification of RISCV Infra System IP.
What you'll do
- Develop test plans and test cases for design feature sets.
- Follow up on code coverage and functional coverage closure at various test bench levels.
- Debug regression signatures and identify bug fixes.
- Work closely with System Architects, Design, and emulation teams on failure debugs and coverage closure.
What you'll need
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field and 3+ years of Hardware Engineering or related work experience OR Master's degree and 2+ years OR PhD and 1+ year.
- 3 to 15 years of experience in IP/Sub System design verification.
- Expertise in UVM, System Verilog DV test bench, Checkers, Trackers, Scoreboards, Assertion, and Functional Coverage.
- Understanding of bus protocols like CHI, AHB, AXI, ACE, ACE-Lite, and Interconnect concepts.
- Knowledge of ARM / RISCV system architecture, Memory Management, Virtual Memory concepts, Core sight architecture, and power management fundamentals.
Nice to have
- Post-Silicon bring-up and HW-SW debug experience.
- Proficiency in Scripting languages (Python or Perl) for Automation initiatives.
Skills: UVM, System Verilog, DV test bench, functional coverage, RISCV system architecture, bus protocols
This role has been open 7 days — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1138
|
Median days open
57 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1138 roles · 92 employers) |
|---|---|---|
| Open roles in this specialty | 107 | 1138 |
| Open roles in the wider Digital Design & Verification family | 381 | 3022 · 114 employers |
| Median days open | 51 d | 57 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: UVM, System Verilog, DV test bench, functional coverage, RISCV system architecture, bus protocols
Who's hiring in this category
- Qualcomm (this employer) · 107 open roles · median 51 d
- AMD · 98 open roles · median 33 d
- NVIDIA · 90 open roles · median 66 d
- Micron Technology · 56 open roles · median 97 d
- Synopsys · 56 open roles · median 24 d
- SiFive · 51 open roles · median 45 d
How we counted: 1138 open Design Verification (Design Verification) roles from 92 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.