RISCV CPU Design Verification Principal Manager/ Engineer - Bangalore, India
Originally posted 17 September 2026 by the employer — open 1 day.
This role focuses on verifying high performance and low power RISC V based CPUs.
About the role
This role involves the verification of high performance and low power RISC V based CPUs. You will develop and execute verification plans for units and features of a CPU design.
What you'll do
- Develop and execute verification plans for units and features of a CPU design.
- Use simulation and formal verification methodologies to execute test plans and develop testbench components like checkers, assertions, stimulus generators.
- Work closely with system architects, design team, software teams, and SoC team to validate system use cases.
- Work closely with the emulation team to enable verification on emulators and FPGA platforms.
- Debug and triage failures in simulation, emulation, and/or Silicon.
- Implement assembly and C language tests for verifying CPU architecture.
What you'll need
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field and 8+ years of Hardware Engineering or related work experience; OR Master's degree in Computer Science, Electrical/Electronics Engineering, or related field and 7+ years of Hardware Engineering or related work experience; OR PhD in Computer Science, Electrical/Electronics Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
- Experience in C/C++, scripting languages, HDLS like Verilog/System Verilog.
- Good understanding of CPU architectures and CPU micro-architectures.
- Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling.
Nice to have
- Strong understanding of power management features in CPUs and CPU based SoCs.
- In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture.
- Experience with advanced verification techniques such as formal and assertions.
- Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump.
- Industry experience with CPU architecture (e.g., x86, ARM, MIPS, RISCV, POWER).
Skills: RISC V CPU, verification plans, simulation, formal verification, testbench
This role has been open 1 day — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1138
|
Median days open
57 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1138 roles · 92 employers) |
|---|---|---|
| Open roles in this specialty | 107 | 1138 |
| Open roles in the wider Digital Design & Verification family | 381 | 3022 · 114 employers |
| Median days open | 51 d | 57 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: RISC V CPU, verification plans, simulation, formal verification, testbench
Who's hiring in this category
- Qualcomm (this employer) · 107 open roles · median 51 d
- AMD · 98 open roles · median 33 d
- NVIDIA · 90 open roles · median 66 d
- Micron Technology · 56 open roles · median 97 d
- Synopsys · 56 open roles · median 24 d
- SiFive · 51 open roles · median 45 d
How we counted: 1138 open Design Verification (Design Verification) roles from 92 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.