RFIC Layout & Design Automation - US-CA-Calabasas, United States
$129,450 - $215,740 USD yearly
Originally posted 15 October 2026 by the employer.
About the role
This R&D Engineer role develops layout and design automation technologies for RFIC, analog, and microwave applications, focusing on RFIC layout, parameterized layout generation, and layout automation complemented by Python-based automation.
What you'll do
- Develop RFIC, analog, and microwave layouts, including parameterized and reusable layout structures.
- Develop automated parameterized layout generation capabilities that translate circuit and design parameters into design-rule-compliant physical layouts.
- Design and implement layout automation including geometry generation, placement, routing, symmetry, design-rule constraints, and EM-aware design.
- Integrate layout generation with circuit and EM simulation to support parameter exploration, design-space analysis, and optimization.
- Develop Python-based tools and scalable software for automated layout and design workflows.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, or a related discipline.
- Strong hands-on experience in RFIC, analog, microwave, or mixed-signal layout and design.
- Experience with RFIC passive and active components such as inductors, transformers, transmission lines, filters, matching networks, mixers, and power amplifiers.
- Deep hands-on experience in parameterized layout generation and PCell development.
- Strong understanding of semiconductor layout methodologies, design rules, physical verification, parasitics, and EM-aware design practices.
- Strong programming experience in Python.
Nice to have
- Experience with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn.
- Knowledge of surrogate modeling, design-space exploration, Bayesian optimization, or other optimization techniques.
- Familiarity with ADS, Cadence Virtuoso, EM simulation tools, or similar EDA platforms.
- Experience applying machine learning or intelligent optimization to semiconductor design workflows.
- Experience working in Agile software development environments.
Skills: RFIC layout, parameterized layout, layout automation, Python, PCell development, EM simulation
This role has been open 0 days — well below the 78-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
688
|
Median days open
78 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (688 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 688 |
| Open roles in the wider Physical Implementation family | 39 | 1459 · 108 employers |
| Median days open | 48 d | 78 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: RFIC layout, parameterized layout, layout automation, Python, PCell development, EM simulation
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 168 d
- Synopsys · 65 open roles · median 38 d
- Micron Technology · 44 open roles · median 80 d
- Qualcomm · 41 open roles · median 66 d
- NVIDIA · 39 open roles · median 79 d
- GlobalFoundries · 33 open roles · median 35 d
How we counted: 688 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.