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Navitas Semiconductor

Reliability Engineer - Pune, India

Navitas Semiconductor Pune, India 19 days ago
Product Engineering & Quality

About the role

This role involves defining, planning, and executing comprehensive qualification testing for high-voltage GaN HEMTs and SiC MOSFETs.

What you'll do

  • Define, plan, and execute qualification testing for high-voltage GaN HEMTs and SiC MOSFETs to meet industrial and automotive standards (JEDEC, AEC-Q101, and AQG324).
  • Conduct Failure mode and effects analysis and root cause analysis on failed devices, investigating and mitigating WBG-specific degradation modes.
  • Partner with device design, process integration, and Failure Analysis (FA) teams to isolate root causes of device failure and implement physical corrective actions.
  • Manage external reliability test execution, including test plan communication, sample logistics, stress condition verification, data collection, and schedule tracking.
  • Operate electrical lab bench instrumentation, including oscilloscopes, function generators, programmable power supplies, digital multimeters, electronic loads, and in-situ DAQ systems.
  • Identify, evaluate, and qualify new suppliers for PCB fabrication, assembly, tooling, and test services.

What you'll need

  • Bachelor’s degree in engineering (Electrical Engineering, Mechanical Engineering, Materials Science, Semiconductor Engineering) or a closely related technical discipline.
  • Minimum 3 years of hands-on experience in semiconductor reliability testing, electrical characterization, qualification execution, failure analysis support, or engineering lab operations.
  • Familiarity with JEDEC standards including Burn-in, Temperature Cycling, Temperature Humidity Bias, HAST, MSL, Power Cycle.
  • Foundational understanding of semiconductor device physics, specifically high-voltage power devices, p-n junctions, and wide bandgap material properties.
  • Ability to interpret and technically review qualification circuits, including biasing schemes, stress-condition implementation, device connections, protection elements, measurement points, and test-fixture interfaces.
  • Some knowledge of PCB schematic and layout tools such as Cadence or Altium, including schematic capture review, component placement assessment, routing and stack-up review, design-rule verification, and fabrication/assembly package generation.

Skills: qualification testing, GaN HEMTs, SiC MOSFETs, JEDEC, AEC-Q101, root cause analysis

Market context

This role has been open 37 days — well below the 54-day median for Reliability Engineering roles.

Reliability Engineering · Reliability Engineering

Open roles in category
410
Median days open
54 d
Median salary
$158k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Navitas Semiconductor compares in Reliability Engineering hiring
Metric Navitas Semiconductor All employers we track in this specialty (410 roles · 71 employers)
Open roles in this specialty 4 410
Open roles in the wider Process, Fab & Equipment family 8 9348 · 109 employers
Median days open 65 d 54 d (+11 d vs this employer)
Median salary (USD postings) — $158k

Skills observed across this category: qualification testing, GaN HEMTs, SiC MOSFETs, JEDEC, AEC-Q101, root cause analysis

Who's hiring in this category

  • Micron Technology · 72 open roles · median 132 d
  • Infineon Technologies · 28 open roles · median 48 d
  • Applied Materials · 24 open roles · median 79 d
  • onsemi · 21 open roles · median 61 d
  • Analog Devices · 20 open roles · median 35 d
  • Renesas Electronics · 19 open roles · median 29 d

How we counted: 410 open Reliability Engineering (Reliability Engineering) roles from 71 employers tracked in the SemiconductorJobs index, counted 16 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.

Apply now
Pune, India
On-site
19 days ago

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