Radiation Effects & RAS Silicon Architect - CA, San Jose, United States
Originally posted 3 September 2026 by the employer.
Contribute to FPGA and SoC architecture definition and development with a focus on radiation effects and RAS.
About the role
This role involves contributing to FPGA and SoC architecture definition and development with a focus on radiation effects and RAS within the Advanced Architecture, Technology & Verification Group. The team focuses on the architecture, development, and validation of commercial and radiation tolerant FPGA/ACAP solutions for Terrestrial and Space markets, with corporate responsibility for Single Event Effects (SEE), radiation effects, and RAS mitigation solutions.
What you'll do
- Apply IC Design and Solid State Physics fundamentals to develop solutions for Single Event Effects (SEE), including SEU, SEL, and SEFI, for FPGAs and space-grade silicon. - Define and develop SEE PDKs (Product Design Kits), test vehicles, and system-level radiation hardening solutions; evaluate test vehicles at the FPGA level. - Contribute to the architecture definition of XQR/Space-grade FPGA and SoC products, including SEE/RAS architectural specifications. - Analyze semiconductor technology scaling and its impact on radiation sensitivity. - Build predictive models for radiation performance, including competitive feature sets, power, and cost trade-offs. - Collaborate with Silicon Technology, Advanced Architecture, and Marketing teams.
What you'll need
- Master's or PhD degree in Electrical Engineering, Applied Physics or equivalent. - Passion for modern, complex silicon architecture and innovation in radiation effects and RAS for terrestrial and space applications. - Experience collaborating with engineers located in different sites/timezones. - Strong analytical and problem-solving skills. - Willingness to learn and take on problems.
Nice to have
- Experience at a semiconductor company in advanced silicon process technologies and architectures. - Deep knowledge of radiation effects (SEU, SEL, SEFI, TID), including underlying physics and impact on semiconductor devices and FPGAs. - Knowledge of FPGA and SoC architecture, implementation, and software tools. - Self-driven, able to set direction and execute independently. - Willingness to travel to worldwide test facilities and development consortia.
Skills: radiation effects, RAS mitigation, FPGA/SoC architecture, Single Event Effects, semiconductor devices
This role has been open 41 days — well below the 79-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
470
|
Median days open
79 d
|
Median salary
$235k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (470 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 470 |
| Open roles in the wider Digital Design & Verification family | 255 | 3188 · 115 employers |
| Median days open | 64 d | 79 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $235k |
Skills observed across this category: radiation effects, RAS mitigation, FPGA/SoC architecture, Single Event Effects, semiconductor devices
Who's hiring in this category
- Qualcomm · 72 open roles · median 86 d
- NVIDIA · 56 open roles · median 68 d
- Apple · 39 open roles · median 9 d
- AMD (this employer) · 35 open roles · median 64 d
- Arm Holdings · 27 open roles · median 112 d
- NXP Semiconductors · 21 open roles · median 114 d
How we counted: 470 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.