R&D Process Engineer - Wafer Wet Process Engineer - US-CA-Santa Rosa-Bldg 2, United States
$138,960 - $231,600 USD yearly
Originally posted 25 June 2026 by the employer.
Fabricate passive interposer substrates for Heterogeneous Integration technology at Keysight's High Frequency Technology Center.
About the role
The High Frequency Technology Center (HFTC) is seeking an R&D Process Engineer to develop, maintain, and optimize manufacturing processes to fabricate passive interposer substrates for Heterogeneous Integration technology. The position owns process development, manufacturing sustainability, and R&D support for new product introductions across wafer fab wet processes.
What you'll do
- Own and advance performance across wet processes, Chemical Mechanical Planarization (CMP), Wet Etch/Clean, Solvent Stripping, and Electroplating by driving quality, chamber health, defect reduction, and yield improvement through structured DOEs. - Collaborate with equipment engineering on tool performance optimization, preventive-maintenance strategies, throughput enhancements, and new tool installs or upgrades. - Drive process control and stability through SPC charting, daily reviews, root-cause analysis, and corrective actions using statistical tools such as JMP. - Define process flows, develop new processes, and execute continuous process improvement (CPI) efforts in partnership with integration, product, and circuit design engineers. - Lead capital equipment acquisition projects encompassing tool evaluation, characterization, process development, and qualification. - Implement robust process controls with Operations and ensure seamless process handoffs to manufacturing partners.
What you'll need
- M.S. or Ph.D. in Materials Science, Chemical Engineering, Physics, Chemistry, or a related field. - 5+ years of professional, hands-on experience as a process engineer developing or maintaining semiconductor wet processes and equipment. - Hands-on expertise with wafer process hardware systems for CMP, Solvent Stripping, Wet Etch, or Electroplating. - Working knowledge of chemical handling systems, including pumps, flow monitoring and control, filters, CMP-specific systems, and chamber-hardware configurations. - Demonstrated experience utilizing statistical process control (SPC) and design of experiments (DOE). - U.S. Person status (U.S. citizen, lawful permanent resident, refugee, or asylee) under U.S. export control laws and regulations.
Skills: wafer wet processes, CMP, wet etch, electroplating, SPC, DOE
This role has been open 119 days — well above the 72-day median for Process Engineering roles.
Process Engineering · Semiconductor Process
|
Open roles in category
1056
|
Median days open
72 d
|
Median salary
$137k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (1056 roles · 56 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 1056 |
| Open roles in the wider Process, Fab & Equipment family | 129 | 10119 · 106 employers |
| Median days open | 28 d | 72 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $137k |
Skills observed across this category: wafer wet processes, CMP, wet etch, electroplating, SPC, DOE
Who's hiring in this category
- Micron Technology · 350 open roles · median 134 d
- GlobalFoundries · 84 open roles · median 86 d
- Applied Materials · 78 open roles · median 70 d
- Texas Instruments · 59 open roles · median 51 d
- STMicroelectronics · 53 open roles · median 45 d
- Entegris · 44 open roles · median 40 d
How we counted: 1056 open Process Engineering (Semiconductor Process) roles from 56 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.