R&D Engineering, Staff Engineer
Originally posted 20 October 2026 by the employer.
About the role
Staff Engineers in this role develop and enhance clock tree synthesis and clock optimization algorithms within Fusion Compiler. The position focuses on core R&D across advanced process nodes from 16nm to 5nm to improve timing closure, skew balancing, and power.
What you'll do
- Develop and enhance clock tree synthesis and clock optimization algorithms in Fusion Compiler, focusing on skew balancing, useful skew, buffering strategies, and insertion delay optimization. - Debug timing and clocking issues in customer designs across advanced process nodes (16nm to 5nm), identify root causes, and translate findings into product improvements. - Design and prototype new CTS and post-CTS optimization flows to improve quality of results, runtime, and convergence predictability. - Implement and test new features in C++, Python, and Tcl across large codebases. - Analyze clock architecture tradeoffs including skew, latency, OCV-aware optimization, and uncertainty. - Collaborate directly with R&D engineers, Customer Application Engineers, and Account Consultants to align product direction with customer requirements.
What you'll need
- Master's degree in Computer Science, Computer Engineering, Electronics Engineering, Mathematics, or a related field with 2+ years of professional experience, or a Ph.D. in a related field. - Strong proficiency in C++ for performance-critical algorithm development and systems software. - Experience with clock tree synthesis, static timing analysis, timing closure, or physical synthesis flows in an EDA or semiconductor design context. - Understanding of clock architecture concepts including skew, latency, insertion delay, transition, uncertainty, and OCV-aware optimization. - Familiarity with VLSI processes and physical design methodology, including timing, area, power, congestion, and signal integrity tradeoffs. - Working knowledge of Python and Tcl for scripting, automation, and tool integration.
Nice to have
- Experience with advanced technology nodes (16nm to 5nm), including finFET and gate-all-around processes.
Skills: clock tree synthesis, Fusion Compiler, C++, skew balancing, timing closure
This role has been open 0 days — well below the 72-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
674
|
Median days open
72 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (674 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 674 |
| Open roles in the wider Physical Implementation family | 107 | 1464 · 110 employers |
| Median days open | 40 d | 72 d (−32 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: clock tree synthesis, Fusion Compiler, C++, skew balancing, timing closure
Who's hiring in this category
- Cadence Design Systems · 154 open roles · median 152 d
- Synopsys (this employer) · 61 open roles · median 39 d
- Micron Technology · 45 open roles · median 49 d
- Qualcomm · 36 open roles · median 78 d
- GlobalFoundries · 34 open roles · median 37 d
- Keysight Technologies · 32 open roles · median 75 d
How we counted: 674 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.