R&D Engineering, Sr Staff Engineer
Originally posted 19 August 2026 by the employer.
Design memory IP at Synopsys, enabling advanced chips in AI, mobile, automotive, and data center applications.
About the role
This role involves designing and developing CMOS embedded memories including SP SRAM, DP SRAM, Register Files, and ROM, as well as owning architecture definition and circuit implementation for memory compilers.
What you'll do
- Design and develop CMOS embedded memories including SP SRAM, DP SRAM, Register Files, and ROM across ultra high speed, ultra low power, and high density design portfolios.
- Own architecture definition and circuit implementation for memory compilers, making critical tradeoffs for performance, area, and yield.
- Perform schematic entry, circuit simulation using SPICE-based tools, layout planning, and supervise physical layout teams through design closure.
- Develop and verify bit cells from initial topology exploration through full layout verification, including parasitic extraction and post-layout simulation.
- Interface directly with CAD teams to automate memory compiler flows and with frontend engineers to generate EDA models and enable full verification integration.
- Lead and mentor junior engineers and trainees on memory design methodology, circuit techniques, and verification best practices.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Electronics, Telecommunications, or a related technical field.
- 8+ years of hands-on CMOS memory design experience with production tapeout responsibility.
- Deep proficiency in memory circuit design, SPICE simulation, layout planning, parasitic extraction, and layout verification tools.
- Strong scripting capability in C-Shell and Perl.
- Demonstrated experience developing bit cells and driving physical layout design through to verification closure.
- Experience interfacing with memory compiler automation flows and EDA model generation.
- Proven ability to lead technical projects and mentor junior engineers through complex design challenges.
Nice to have
- Experience with C++ or JavaScript.
Skills: CMOS memory design, SRAM, bit cell layout, SPICE simulation, layout planning, parasitic extraction
This role has been open 45 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 287 |
| Median days open | 49 d | 69 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: CMOS memory design, SRAM, bit cell layout, SPICE simulation, layout planning, parasitic extraction
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys (this employer) · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.