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Synopsys

R&D Engineering, Sr Manager

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Noida, India 1 month ago
Digital Design & SoC Architecture

Originally posted 30 August 2026 by the employer.

About the role

This role involves leading an engineering team focused on the architecture and circuit implementation of embedded memory products such as SRAM, Register File, TCAM, and ROM.

What you'll do

  • Lead a team developing SRAM, Register File, TCAM, and ROM architectures and circuit implementations across advanced FinFET nodes.
  • Oversee the full memory design flow from architecture definition through schematic entry, simulation, layout planning, verification, characterization, and model generation.
  • Drive low-power and area-efficient circuit design strategies, balancing performance, variation, and manufacturability constraints.
  • Coordinate with CAD teams on layout verification, parasitic extraction, and compiler automation using Perl and Python.
  • Manage project timelines, prioritize deliverables, and resolve technical and resourcing issues across multi-site teams.
  • Mentor engineers on memory compiler development, transistor-level design, and advanced node challenges.

What you'll need

  • BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering.
  • 15+ years of hands-on experience in embedded memory design, including SRAM, Register File, TCAM, or ROM.
  • Deep expertise across the full memory design flow: architecture, circuit design, layout, compiler automation, characterization, timing, and model generation.
  • Proven experience leading engineering teams and delivering complex projects on schedule in a multi-site environment.
  • Strong proficiency in Perl and Python for design automation and scripting.
  • Hands-on experience with deep submicron and FinFET technologies, including variation-aware design techniques.
  • Solid understanding of CMOS fundamentals, digital design, RC circuits, transfer function analysis, and CMOS fabrication processes.

Skills: embedded memory, SRAM, Register File, TCAM, ROM, FinFET

Market context

This role has been open 35 days — well below the 69-day median for Memory Design roles.

Memory Design · Memory Design

Open roles in category
287
Median days open
69 d
Median salary
$205k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Synopsys compares in Memory Design hiring
Metric Synopsys All employers we track in this specialty (287 roles · 29 employers)
Open roles in this specialty 27 287
Median days open 49 d 69 d (−20 d vs this employer)
Median salary (USD postings) — $205k

Skills observed across this category: embedded memory, SRAM, Register File, TCAM, ROM, FinFET

Who's hiring in this category

  • Micron Technology · 151 open roles · median 86 d
  • Synopsys (this employer) · 27 open roles · median 49 d
  • SanDisk · 17 open roles · median 32 d
  • Broadcom · 16 open roles · median 50 d
  • Qualcomm · 12 open roles · median 149 d
  • NVIDIA · 7 open roles · median 59 d

How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Noida, India
On-site
1 month ago

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