R&D Engineering, Director
Originally posted 25 August 2026 by the employer.
About the role
As R&D Engineering, Director, you will lead a team that builds embedded memory IP.
What you'll do
- Lead a team of memory design engineers developing SRAM, Register File, TCAM, and ROM architectures and circuit implementations for advanced process nodes including FinFET.
- Own the full memory design flow from bit cell analysis and architecture through schematic entry, simulation, layout planning, characterization, verification, and model generation.
- Drive low-power, area-efficient embedded memory circuit design and supervise layout activities, interfacing directly with CAD teams on verification and compiler automation.
- Manage project timelines, prioritize tasks across multiple concurrent projects, and resolve technical and scheduling issues proactively to ensure on-time delivery.
- Build and maintain relationships with cross-functional teams including characterization, verification, and customer-facing engineering to align on deliverables and resolve escalations.
- Apply and expand expertise in memory compiler development, transistor-level circuit design, and variation-aware design techniques for deep submicron technologies.
What you'll need
- BE/B.Tech/ME/M.Tech/MS in Electrical and Electronics Engineering.
- 20+ years of hands-on experience in embedded memory design including SRAM, Register File, TCAM, and ROM architecture and circuit implementation.
- Deep expertise across the full memory design flow: architecture, schematic design, layout planning, characterization, timing analysis, and model generation.
- Proven experience leading and managing engineering teams, delivering complex projects on schedule, and resolving technical and project issues across multiple priorities.
- Strong proficiency in transistor-level circuit design for deep submicron and FinFET technologies, including variation-aware design techniques.
- Mastery of Perl and Python for design automation and scripting.
Skills: embedded memory IP, SRAM, Register File, TCAM, bit cell analysis, memory compiler
This role has been open 39 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 27 | 287 |
| Median days open | 49 d | 69 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: embedded memory IP, SRAM, Register File, TCAM, bit cell analysis, memory compiler
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys (this employer) · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.