R&D Engineering, Director-18881

Originally posted 30 September 2026 by the employer.

About the role

This role involves defining and driving corporate and customer-facing DFT methodologies for ASIC and SoC designs, focusing on the successful adoption of Synopsys TestMAX® solutions.

What you'll do

• Define and drive corporate and customer-facing DFT methodologies for ASIC and SoC designs.
• Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies.
• Architect scalable test access and instrumentation networks leveraging IEEE 1149.1, IEEE 1149.6, IEEE 1687 (IJTAG), and IEEE 1500 standards.
• Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
• Drive adoption of reusable methodologies, automation frameworks, and signoff criteria across multiple programs and business units.
• Provide technical leadership for strategic customer engagements, methodology reviews, and complex technical escalations.

What you'll need

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of experience in Semiconductor or EDA industry with a focus on DFT, ATPG, and manufacturing test methodologies.
• Demonstrated expertise in architecting and implementing DFT solutions for large-scale ASIC and SoC designs.
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
• Strong understanding of scan insertion, scan compression, hierarchical DFT methodologies, ATPG, diagnosis, stuck-at, transition, path-delay, bridge, and cell-aware fault models, coverage analysis and optimization, test cost and pattern count reduction techniques.
• Expertise with standards including IEEE 1149.1 (JTAG), IEEE 1149.6 (AC JTAG), IEEE 1687 (IJTAG), and IEEE 1500.
• Experience developing and deploying JTAG / TAP Architectures, Boundary Scan Networks, IJTAG Instrumentation Networks, Embedded Instrument Access Solutions.
• Expertise in deploying and integrating DFT IP including Codec / Embedded Compression, OCC (On-Chip Clock Controller), LBIST, TAP Controllers, JTAG and IJTAG Infrastructure, TDR Networks, IEEE 1500 Wrappers.
• Strong understanding of RTL-to-GDSII implementation flows and interactions between DFT, synthesis, physical design, timing closure, and signoff.
• Proficiency with Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation.

Nice to have

• Recognized expert in DFT architecture and test methodology deployment.
• Experience defining enterprise-wide DFT standards and signoff methodologies.
• Strong background supporting advanced-node ASICs and multi-billion gate SoCs.
• Experience with silicon bring-up, diagnosis, yield improvement, and production ramp.
• Knowledge of functional safety standards and test requirements for automotive applications.
• Experience collaborating directly with semiconductor customers in applications engineering, consulting, or methodology leadership roles.
• Contributions to industry test standards, technical publications, patents, or conference presentations.

Skills: DFT, ATPG, scan compression, IJTAG, TestMAX