R&D Engineer Simulation software - US-CA-Santa Clara-Bldg 2-Keysi, United States
$156,960 - $261,600 USD yearly
Originally posted 9 July 2026 by the employer.
About the role
This role develops and improves the core simulation engine behind Keysight's circuit simulation products. The Circuit Simulation R&D team focuses on simulation technologies used to design RF, microwave, analog, mixed-signal, and high-speed electronic systems.
What you'll do
- Provide technical leadership in the development of advanced circuit simulation algorithms. - Investigate fundamental simulation challenges involving accuracy, convergence, performance, and scalability. - Develop numerical algorithms for nonlinear circuit analysis and differential equation solving. - Improve solver technologies, including sparse matrix algorithms, nonlinear solution methods, and numerical integration techniques. - Evaluate and introduce methods for simulation acceleration, including model order reduction, RC reduction, vector fitting, and parallel computation. - Analyze simulation performance and identify opportunities for improvements in runtime and memory efficiency.
What you'll need
- Advanced degree in Electrical Engineering, Electrical Engineering and Computer Science (EECS), Computer Science, Applied Mathematics, Computational Science, or a related field. - Extensive experience developing circuit simulation engines, numerical simulation software, or other large-scale scientific computing applications. - Strong knowledge of nonlinear equation solving, Newton-Raphson methods, convergence techniques, and differential equation analysis. - Deep understanding of sparse matrix algorithms and numerical linear algebra. - Expert-level programming skills in C++ with experience developing large, maintainable software systems. - Ability to analyze complex simulation behavior and translate mathematical concepts into reliable software implementations.
Nice to have
- Master's or Ph.D. degree. - Expertise in transient (TRAN) simulation techniques and numerical integration methods, including Adaptive timestep control, Backward Euler, Trapezoidal, Gear integration methods, Local truncation error estimation, or Convergence acceleration techniques. - Experience with sparse solver technologies, such as Matrix ordering, Sparse factorization, and Iterative and direct linear solvers. - Experience in model order reduction, parasitic reduction, semiconductor device modeling, or high-performance computing. - Experience using Python or Rust for prototyping, automation, and engineering productivity.
Skills: circuit simulation, numerical algorithms, solver technologies, sparse matrix, C++
This role has been open 103 days — well above the 72-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
674
|
Median days open
72 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (674 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 32 | 674 |
| Open roles in the wider Physical Implementation family | 39 | 1441 · 110 employers |
| Median days open | 74 d | 72 d (+2 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: circuit simulation, numerical algorithms, solver technologies, sparse matrix, C++
Who's hiring in this category
- Cadence Design Systems · 154 open roles · median 152 d
- Synopsys · 61 open roles · median 39 d
- Micron Technology · 45 open roles · median 49 d
- Qualcomm · 36 open roles · median 78 d
- GlobalFoundries · 34 open roles · median 37 d
- Keysight Technologies (this employer) · 32 open roles · median 75 d
How we counted: 674 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.