R&D DSP/FPGA Design Automation Intern
Originally posted 4 November 2026 by the employer.
About the role
This R&D intern will help develop and demonstrate a scalable, AI-assisted development workflow for FPGA-based digital signal processing systems. The role spans signal processing, digital design, and software automation across the FPGA development lifecycle.
What you'll do
- Build reusable, parameterized FPGA components for DSP, including MACs, FIFOs, adder trees, coefficient memories, delay elements, and numeric conversion blocks.
- Translate DSP and system requirements into FPGA architecture and implementation specifications.
- Design and verify RTL in Verilog, SystemVerilog, VHDL, or an equivalent language, and write bit-accurate or fixed-point reference models.
- Assemble components into a streaming DSP subsystem and create automated simulation and verification tests for numerical accuracy, reset behavior, streaming interfaces, and backpressure.
- Support synthesis, timing analysis, resource evaluation, and optimization.
- Use Python or similar languages to automate design, testing, data collection, and reporting while investigating AI-assisted development tools.
What you'll need
- Currently pursuing a Bachelor's or Master's degree in EE, CE, CS, or a related field.
- Coursework, project work, or job experience in DSP or digital system design.
- Understanding of digital logic, synchronous design, pipelining, and FSMs.
- Experience with at least one HDL or hardware-construction language such as Verilog, SystemVerilog, VHDL, or Chisel.
- Experience with Python, MATLAB, C/C++, or a similar language for modeling or automation.
- Familiarity with fixed-point arithmetic, quantization, or numerical implementation of DSP algorithms.
Nice to have
- Experience designing, simulating, or synthesizing FPGA logic with Xilinx/AMD, Intel, or comparable tools.
- Experience with streaming interfaces (valid/ready, FIFOs, clock domains).
- Experience implementing FIR filters, resamplers, channelizers, or other waveform processing.
- Experience writing parameterized, reusable HDL.
- Experience with cocotb, constrained-random testing, assertions, or formal verification.
- Experience with Git, CI, automated builds, regression testing, or building software tools.
- Experience using AI-assisted tools for software, HDL, testing, or analysis.
More semiconductor jobs: Keysight Technologies jobs · FPGA engineer jobs
This role has been open 0 days — well below the 64-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
108
|
Median days open
64 d
|
Category median salary (all employers)
$163k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Keysight Technologies | All employers we track in this specialty (108 roles · 23 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 108 |
| Median days open | 12 d | 64 d (−52 d vs this employer) |
| Median salary (USD postings) | — | $163k |
Who's hiring in this category
- Altera · 37 open roles · median 54 d
- AMD · 13 open roles · median 62 d
- Teradyne · 8 open roles · median 87 d
- Keysight Technologies (this employer) · 7 open roles · median 11 d
- Microchip Technology · 6 open roles · median 85 d
- Qualcomm · 6 open roles · median 86 d
How we counted: 108 open FPGA Design (RTL Design) roles from 23 employers tracked in the SemiconductorJobs index, counted 4 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.