Quantum Compute Wafer and Device Characterization Engineer - San Jose, United States
Originally posted 9 October 2026 by the employer.
About the role
This role focuses on quantum compute wafer level characterization, with an emphasis on detailed surface, interfaces, and thin film materials characterization for superconducting qubit nanofabrication.
What you'll do
- Lead research projects in quantum computing wafer and device level characterization.
- Execute thin film materials stack characterization and resonator and qubit device room temperature characterization.
- Utilize various surface and interface characterization techniques.
- Collaborate with product teams to develop solutions.
- Develop and present detailed reports and visualizations to stakeholders.
- Independently pursue fundamental research, including paper writing and publishing.
What you'll need
- Ph.D degree and post-doctoral experience in Physics, Electrical Engineering, Materials Science with focus on thin film characterization, as well as surface and interfaces characterization of thin film materials stacks for superconducting qubits.
- Thorough understanding of superconducting qubit design.
- Experience in thin film materials characterization including XRD, AFM, CIPT, SEM, cross-sectional TEM, XPS, AES, ESCA, TOF-SIMS.
- Proficiency in programming languages like Python, Rust, TCL, or C.
- Knowledge (or willingness to acquire knowledge) of FPGA based microcontrollers.
Nice to have
- Experience in nanofabrication methods for superconducting qubits.
This role has been open 0 days — well below the 24-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
523
|
Median days open
24 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Western Digital | All employers we track in this specialty (523 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 523 |
| Open roles in the wider Silicon Validation & Test family | 15 | 2209 · 111 employers |
| Median days open | 2 d | 24 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Who's hiring in this category
- Teradyne · 67 open roles · median 21 d
- Infineon Technologies · 39 open roles · median 35 d
- Renesas Electronics · 39 open roles · median 24 d
- AMD · 28 open roles · median 36 d
- Micron Technology · 28 open roles · median 30 d
- Qualcomm · 25 open roles · median 23 d
How we counted: 523 open Silicon Test Engineering (DFT Test) roles from 75 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.